Electrical computers and digital data processing systems: input/ – Access arbitrating
Reexamination Certificate
2005-12-13
2005-12-13
Rinehart, Mark H. (Department: 2111)
Electrical computers and digital data processing systems: input/
Access arbitrating
C710S309000, C710S306000, C710S113000, C710S114000, C710S115000, C710S116000, C710S117000, C710S118000
Reexamination Certificate
active
06976108
ABSTRACT:
A system on a chip has functional blocks accommodated by at least one system bus, and an external bus for accommodating communication with external blocks. A single multi-jurisdictional bus arbiter has programmable rankings for assigning priorities to requests from blocks that are masters for either one of the both buses. Software and methods are also provided for assigning the priorities. The requests are analyzed with respect to which of the buses they require, and then priorities are assigned to maximize bus utilization, with increased speed for a system on a chip. In addition, a multi-jurisdictional multi-channel direct memory access block can be a master block for the system bus or the external bus.
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Kim Young-sik
Lee Yun-Tae
Marger & Johnson & McCollom, P.C.
Mason Donna K.
Rinehart Mark H.
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