Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral configuration
Reexamination Certificate
2011-08-02
2011-08-02
Hafiz, Tariq (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral configuration
C710S005000, C710S032000, C710S036000
Reexamination Certificate
active
07991922
ABSTRACT:
A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.
REFERENCES:
patent: 4433378 (1984-02-01), Leger
patent: 4463424 (1984-07-01), Mattson et al.
patent: 4760571 (1988-07-01), Schwarz
patent: 5640399 (1997-06-01), Rostoker et al.
patent: 5668809 (1997-09-01), Rostoker et al.
patent: 5778414 (1998-07-01), Winter et al.
patent: 5802287 (1998-09-01), Rostoker et al.
patent: 5802559 (1998-09-01), Bailey
patent: 5829025 (1998-10-01), Mittal
patent: 5859989 (1999-01-01), Olarig et al.
patent: 5887187 (1999-03-01), Rostoker et al.
patent: 5893150 (1999-04-01), Hagersten et al.
patent: 5893153 (1999-04-01), Tzeng et al.
patent: 5908468 (1999-06-01), Hartmann
patent: 5914955 (1999-06-01), Rostoker et al.
patent: 5970069 (1999-10-01), Kumar et al.
patent: 5974508 (1999-10-01), Maheshwari
patent: 6064626 (2000-05-01), Stevens
patent: 6098064 (2000-08-01), Pirolli et al.
patent: 6111859 (2000-08-01), Godfrey et al.
patent: 6122667 (2000-09-01), Chung
patent: 6141376 (2000-10-01), Shaw
patent: 6151662 (2000-11-01), Christie et al.
patent: 6157623 (2000-12-01), Kerstein
patent: 6202125 (2001-03-01), Patterson et al.
patent: 6202129 (2001-03-01), Palanca et al.
patent: 6209020 (2001-03-01), Angle et al.
patent: 6215497 (2001-04-01), Leung
patent: 6223239 (2001-04-01), Olarig
patent: 6226680 (2001-05-01), Boucher et al.
patent: 6266797 (2001-07-01), Godfrey et al.
patent: 6269427 (2001-07-01), Kuttanna et al.
patent: 6332179 (2001-12-01), Okpisz et al.
patent: 6349365 (2002-02-01), McBride
patent: 6366583 (2002-04-01), Rowett et al.
patent: 6373846 (2002-04-01), Daniel et al.
patent: 6438651 (2002-08-01), Slane
patent: 6484224 (2002-11-01), Robins et al.
patent: 6633936 (2003-10-01), Keller et al.
patent: 6633967 (2003-10-01), Duncan
patent: 6636947 (2003-10-01), Neal et al.
patent: 7076568 (2006-07-01), Philbrick et al.
patent: 2003/0038809 (2003-02-01), Peng et al.
Gustavson, David, Scalable Coherent Interface and Related Standards Projects, Sep. 1991, Department of Energy [online, accessed on Mar. 26, 2011] URL: http://www.osti.gov/bridge/purl.cover.jsp;jsessionid=DCEACFB89CCFECAF6BC95490873F5DCA?purl=/5094466-xw8TIN/.
Cho James Y.
Hayter Mark D.
Rowlands Joseph B.
Broadcom Corporation
Garlick & Harrison & Markison
Hafiz Tariq
Sun Scott
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