Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2002-02-25
2004-03-30
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S049130, C365S189020, C365S189050, C365S189070, C365S189080, C365S201000, C365S230020, C365S230060, C365S230080
Reexamination Certificate
active
06714466
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The inventions described and/or claimed in this patent relate in general to a performing a repair analysis for a semiconductor memory device having a redundant architecture. More specifically, they relate to performing a repair analysis for a semiconductor memory device having a redundant architecture capable of simultaneously or synchronously performing a test and a repair analysis for semiconductor memory device and of performing a rearranging operation which moves and exchanges fail address data in a unit row and column thereby enhancing efficiency in utilizing rows and columns.
2. Description of the Background Art
In semiconductor memory devices employing a redundant architectural arrangement, operations for repairing failed memory cells have been usually carried out by an external apparatus using fail address data resulting from a test of all memory cells of the memory device.
Many semiconductor memory devices have a built-in self-test (BIST) arrangement that enables repair operations to be carried out. Such an internal repair function requires space for storing bits of data corresponding to addresses that have been tested and failed the test. This data is known as ‘fail address data’. The storage of this data takes up overhead that could otherwise be used for better purposes, thus contributing to chip inefficiency.
Although a manner for repairing memory cells by testing in the unit of row (or column) has been proposed, it is impossible to perform a repair analysis of a row redundancy or a column redundancy because an algorithm of a repair analysis should be used by one of the row and column redundancy configurations with reference to patterns of fail address data (data for defective cell).
SUMMARY OF THE INVENTION
Among the inventions disclosed and/or claimed, there is provided a semiconductor memory device capable of performing a repair analysis operation synchronously with a test operation in the unit of row or column.
There is also provided a semiconductor memory device capable of enhancing efficiency of a redundancy operation by moving and exchanging fail address data in the unit of row or column the fail address data FAD stored in a CAM.
More specifically, according to at least one embodiment of the various inventions described, there is provided an arrangement for performing a repair analysis. A test unit performs a test operation in a row and column and detects defective cells. A repair analysis means performs a repair analysis operation which causes data to be moved and exchanged between the fail address data assigned to defective cells of a semiconductor memory device in the unit of row and column.
According to another aspect of the various inventions described and/or claimed herein, there is described a method of performing a repair analysis with fail address data assigned to defective cells in a system of a repair analysis. A test operation is carried out for cells of the semiconductor memory device in the unit of row and column. Fail address data for defective cells is stored into a data buffer. The fail address data stored in the data buffer is written into a storage block. Then, fail address data is moved and exchanged to complete the process.
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Kwon Hyeok Man
Mun Joo Hyung
Park Sang Wook
Hynix / Semiconductor Inc.
Nelms David
Pham Ly Duy
Pillsbury & Winthrop LLP
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