System observation bus

Details System observation bus System observation bus

2001-04-09

2004-08-03

Iqbal, Nadeem (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S030000, C714S032000, C714S025000

Reexamination Certificate

active

06772369

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to the field of digital communications and, more particularly, to the test and debug of digital systems.
2. Description of the Related Art
One of the more important aspects of developing electronic and digital systems is that of test and debug. For example, during the design process of a computer system, multiple iterations of test and debug are typically done on various portions of the system prior to actually constructing the system. At some point, a sufficient degree of confidence is obtained in the design and a system utilizing the design is actually constructed. Upon constructing such a system, further test and debug is a necessary part of the process.
Numerous well known methods of test and debug exist for the purpose of debugging circuits and systems subsequent to fabrication. One of the more common tools used in test and debug involves the use of probes. Frequently, during test or debug of a system, the test engineer wishes to observe the behavior of a particular circuit or subsystem during system operation. Because the circuit or subsystem may be embedded in a circuit board or package, access to the circuit or subsystem may be limited. Typically, probes are attached to externally accessible circuit points. In the past, probes may have included alligator clips or spring-loaded oscilloscope grabbers. For the more difficult to access points, flat-ended, toothless alligator clips may have been utilized. However, with the miniaturization of circuits and packaging over the past years, the challenge of probing and testing has grown considerably. Because of the very small pitches of newer packages, attaching probes has become very difficult. Further, newer packaging techniques such as ball grid array (BGA) make it impossible to probe every connection. Therefore, changes to the physical characteristics of the system may be required which could be disruptive of the environment under test. Also, access to external circuit points may not provide details of the internal state of the circuit itself. Rather, only that information which is conveyed via the probed circuit points will be seen. For example, if access is only obtainable to a communication port or bus on a circuit board, the internal state of a particular control circuit or processor on that circuit board may not be observable. Consequently, the test engineer may be limited in his ability to adequately debug the system.
A second method which is sometimes used to gain access to operational and debug information is the use of “windows”. In this context, a window may be defined as a an access point which is deliberately created for the purpose of observation during test and debug. However, such a technique frequently involves the use of dedicated pins which may increase the pin count. Alternatively, a window may be created by multiplexing existing pins to create an observation point. However, such a technique also involves altering the normal design and operational environment. Further, if window pins are captured in a dedicated storage facility, rather than leading to probe points, the gate count of the design may be increased.
A third method of obtaining access to test and debug information is through the use of well known scan based technologies which were developed to address some of the loss of access problems described above. Unfortunately, the capture and shift, pause and stop nature of the scan based testing may also interfere with normal system timing.
In addition to the difficulties discussed above, other challenges exist in test and debug of systems subsequent to fabrication or construction. Because of the desire to test systems as they might appear in the real world, tests engineers are frequently faced with the challenge of working with systems which are fully constructed within a chassis. Consequently, in order to access the internal components of a system, some form of physical access must be created which does not materially interfere with the ordinary operation of the system. If a cut-out is created in the chassis in order to gain access, the normal airflow and cooling of the system may be changed. Consequently, ordinary operation of the system may be altered. Other options may include soldering probe connections to the desired observation points and running connection lines outside the chassis. However, such reworking of circuit boards can be an arduous task and may interfere with the electrical characteristics of the circuitry. Further, these problems may become magnified in the context of multiprocessor computer systems which include densely populated circuit boards. Still further, even if some form of connection access is achieved, the internal state of processors, application specific integrated circuits (ASICs), and other devices may not be obtained by simply observing information conveyed via these accessible circuit points.
In view of the above described problems, as well as others, a method and mechanism of test and debug which primarily utilizes normal and required design constructs without interfering with normal system timing is desired.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a method and mechanism as described herein. In one embodiment, a method for routing observation data to a convenient observation point in a computer system is described. The method includes configuring a node to identify and route observation data via a non-critical path to a predetermined observation point. In one embodiment, the node is configured to generate a data stream which corresponds to the internal state of the device and convey this data stream via the non-critical path to the observation point. Alternately, the node may be configured to duplicate a received data stream, convey the received data stream via a normal operational data path, and convey the duplicated data stream via the non-critical path. Also contemplated is an embodiment wherein the node is configured to identify and extract debug data from within a received data stream, convey the extracted debug data via a non-critical path to an observation point, and convey the remainder of the data stream via a normal operational data path. In general, the non-critical path may comprise dedicated, disabled, replicated, or otherwise non-critical lines, such as error correcting code (ECC) lines which are not required for operation.


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P.K. Jaini and N.A. Touba, “Observing Test Response of Embedded Cores through Surrounding Logic”, Proc. of IEEE International Symposium on Circuits and Systems, pp. 119-123, 1999.
Jan Håkegård:Board Level Boundary Scan Testing and Test Controllers, CADLAB Memo 95-01, Department of Computer and Information Science, Linköping University, 1995.

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