Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2005-12-27
2008-08-12
Peyton, Tammara R (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S051000, C710S054000, C710S053000, C710S055000, C370S365000, C370S503000, C370S902000, C370S395430
Reexamination Certificate
active
07412546
ABSTRACT:
A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.
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Basso Claude
Calvignac Jean Louis
Heddes Marco C.
Logan Joseph Franklin
Verplanken Fabrice Jean
Cockburn Joscelyn G.
Del Zoppo, III Anthony M.
Driggs, Hogg, Daugherty & Del Zoppo Co., LPA
International Business Machines - Corporation
Peyton Tammara R
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