Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-10-02
2007-10-02
Lane, Jack (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S119000, C710S100000, C710S305000
Reexamination Certificate
active
10977846
ABSTRACT:
A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the downstream memory bus and the upstream memory bus. The first memory module and the memory controller are in direct communication via the upstream memory bus and the downstream memory bus.
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Gower Kevin C.
Kellogg Mark W.
Maule Warren E.
Smith, III Thomas B.
Tremaine Robert B.
Augspurger Lynn
Cantor & Colburn LLP
Lane Jack
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