Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2007-11-13
2007-11-13
Sough, Hyung (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S115000, C711S154000, C711S156000, C711S157000, C711S170000, C711S101000, C710S100000, C710S313000, C365S063000
Reexamination Certificate
active
10903178
ABSTRACT:
A packetized cascade memory system including a plurality of memory assemblies, a memory bus including multiple segments, a bus repeater module and a segment level sparing module. The bus repeater module is in communication with two or more of the memory assemblies via the memory bus. The segment level sparing module provides segment level sparing for the communication bus upon segment failure.
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Gower Kevin C.
Kark Kevin W.
Kellogg Mark W.
Maule Warren E.
Augspurger Lynn
Cantor & Colburn LLP
Chery Mardochee
International Business Machines - Corporation
Sough Hyung
LandOfFree
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