Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-04-10
2007-04-10
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C703S016000
Reexamination Certificate
active
10602369
ABSTRACT:
Under the present invention, a proposed placement of I/O pads into one or more groups on a chip analyzed. Specifically, using resources such as a control file, cross-reference table, an I/O limit table, and an optional information file, a group switching current for each proposed I/O pad group is automatically calculated and compared to predetermined maximum switching current(s). If an I/O pad group exhibits a switching current that exceeds its predetermined maximum, corrective action is taken. Such action can include, for example, relocation of an I/O pad from an overloaded I/O pad group to another I/O pad group, insertion of an additional power pad into the overloaded I/O pad group, etc.
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Dotson Michael W.
Wise Matthew D.
Hoffman Warnick & D'Alessandro LLC
Kik Phallaka
Steinberg William H.
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