Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
1998-08-10
2001-08-28
Nguyen, Than (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S105000, C711S171000, C711S172000, C711S173000, C711S213000, C711S217000, C711S218000, C711S219000
Reexamination Certificate
active
06282622
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the field of detecting memory array architectures and in particular to a method, system, and product for detecting row by column structures in Dynamic Random Access Memory arrays.
DRAM is used in a wide variety of memory intensive applications. Consumer electronic devices, for example, phones, electronic organizers, compact disk players, etc., may use DRAM as it is relatively inexpensive and provides relatively fast access. In such devices, memory detection and integrity assurance must occur before the devices may function. Memory detection and integrity assurance are also important when the DRAM is exchanged or replaced, which may occur when upgrading or repairing devices, for example.
One known method of detecting DRAM modules employs detect bits. Detect bits are created when a zero ohm resistor associated with a DRAM module is coupled to a pull up resistor mounted in a receiving socket. When the socket receives the DRAM cell, the zero ohm resistor is coupled to the pull up resistor yielding a low value that uniquely identifies the DRAM's presence. Specific binary codes are created as DRAM modules are received by DRAM sockets.
Another known method of detecting DRAM modules employs serial Electrically Erasable Programmable Read Only Memory (EEPROM). The EEPROMs mount to the DRAM modules and store information relating to the DRAM's speed, size, and configuration.
The use of resistors and EEPROMs to detect memory structure consumes power, may cost valuable board real estate, may identify inaccurate structures, and may increase assembly cost—important considerations for memory applications where size is limited, performance is critical, and low cost is essential.
In light of the strengths and weaknesses of the conventional art, there is a need for a method, system, and product for detecting row by column structures of DRAM arrays. The method, system, and product should circumvent the problem of detecting memory arrays through collateral components while detecting data structures automatically through access routines. There is further need for a method, system, and product that detects memory architecture while assuring memory integrity.
SUMMARY OF THE INVENTION
A method, system, and product for detecting a row by column structure in a Dynamic Random Access Memory array is disclosed. According to a first aspect, the number of columns in a DRAM array is identified by writing data to and reading data from at least one address selected from a first series of cell addresses. The first series of cell addresses identify standard DRAM column structures. When the data written to and read from the cell address is identical, the column configuration of the DRAM arrays is identified. The number of rows in the memory array is then identified by writing data to and reading data from at least one address selected from a second series of cell addresses. The second series of cell addresses identify standard DRAM row structures. When data written to and read from the cell address is identical, the row configuration of the DRAM array is identified and accordingly, the row by column structure of the DRAM array is known.
According to a second aspect, the column structure of the DRAM array is detected by determining a maximum column boundary address, writing data to and reading data from a first memory address corresponding to the maximum column boundary address less a column-modifier, comparing the data read from to the data written to the first memory address, calculating the column-modifier, and then repeating the earlier steps until data read from the first memory address is identical to the data written to the first memory address. The routine next uncovers the row structure of the DRAM array by determining a maximum row boundary address, writing data to and reading data from a second memory address corresponding to the maximum row boundary address less a row-modifier, comparing the data read from to the data written to the second memory address, calculating the row-modifier, and repeating the earlier steps until data read from the second memory address is identical to the data written to the first memory address.
Memory integrity of the DRAM array may be assured in the first or second aspect by writing to and reading from each memory location of the DRAM array.
REFERENCES:
patent: 5003506 (1991-03-01), Itaya
patent: 5179686 (1993-01-01), White
patent: 5278801 (1994-01-01), Dresser et al.
patent: 5386383 (1995-01-01), Raghavachari
patent: 5522062 (1996-05-01), Yamaki
patent: 5600604 (1997-02-01), Chen
patent: 5604880 (1997-02-01), Dipert
patent: 5701438 (1997-12-01), Bains
patent: 5708791 (1998-01-01), Davis
patent: 5802603 (1998-09-01), Bains et al.
patent: 5974501 (1999-10-01), Shaver et al.
patent: 2 066 529 (1981-07-01), None
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