Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-03-28
2004-05-25
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06742165
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to computer network applications, and more particularly to computer network applications which facilitate the design of integrated circuits.
2. Related Art
In today's technological climate, there is a continuing advancement in computing technology and processing power, as well as the increased availability of computing facilities and platforms. Despite such computing technology progress, however, the process of designing integrated circuits has remained stagnant. That is, today's engineers still undergo a mostly manual process when designing and testing integrated circuits (or “chips”) for use in electronic products.
In general, the chip design process can be viewed and explained as a series of six sequential phases: (1) system architecture exploration; (2) software development; (3) design; (4) verification; (5) synthesis, layout and static timing analysis (STA); and (6) auto test pattern generation (ATPG).
First, in the system architecture exploration phase, a chip designer explores different system architectures. Depending on the requirements of the system (i.e., the product) for which the chip is being designed, the chip designer may need to analyze any or all of the following factors: frequency/performance; bus bandwidth and latency; interrupt latency; memory latency and bandwidth; cache size; and software compatibility. Today, much of this is done manually, although using a cycle-accurate simulator sometimes helps. With the advent of multi-million gate SOC (“system on chip” or application specific integrated circuit (ASIC)) designs, the above analyses may be required for multiple cores on a chip.
Second, in the software development phase, the designer makes hardware/firmware/driver determinations for the system. Many different methodologies are now employed. Often, the chip design engineer needs actual hardware to do software development. If this is the case, they must decide whether to purchase standard boards or wait until their chip is actually manufactured before starting software design. In many cases, design engineers desire to start software development simultaneously with hardware development. Conventional tools exist that model hardware behavior in order to enable early software design. Many of these are part of an integrated software development environment (IDE) that offers project management, compilation control and debug functionality. These tools, however, are stand-alone and not integrated into the other five phases of chip design.
Third, in the design phase, the actual register transfer level (RTL) design is typically done as a manual process using pencil and paper, or some computer screen editor (e.g., Emacs). In some cases, a graphical interface may be used to design state machines using state transition diagrams. As will be appreciated by one skilled in the relevant art(s), a state transition diagram consist of circles to represent states and directed line segments to represent transitions between the states, wherein one or more actions (outputs) may be associated with each transition.
Fourth, in the verification phase, design engineers typically utilize simulators to “load” the developed software onto the designed hardware (i.e., the chip). The verification phase, in essence, involves the design engineer determining if the chip functions as called for in the design specification. Such functional verification is computer intensive. Generally speaking, the chip designer submits their design and then executes some type of electronic design automation (EDA) tool (e.g., simulators, formal verifiers or code linters). After the EDA tool is executed, the engineer analyzes the results. These results are in the form of text log files and result files. Then, graphical waveform viewing is also often done after simulations. One shortcoming of this process is that the design engineer must manually submit designs as well as manually verify the rest of the chip design, then manually build a simulation engine. More experienced engineers find this process relatively simple, yet error prone. More novice design engineers, however, find a need to keep careful notes given that the process is fairly detailed and manual.
Fifth, in the synthesis, layout and STA (collectively referred to as the “back-end”) phase, the following user inputs are required: the design database (i.e., the RTL module files); synthesis constraints and compile options; and a floor plan (typically the most important user input to layout and is generated using graphical EDA floor planners). The synthesis is the translation of the RTL to actual logic gate implementations. The layout refers to the actual physical placement of gates onto the silicon wafer. STA is the timing verification of the chip (i.e., “how fast does it run?”). For most projects, synthesis, layout and STA are computationally intensive tasks with little user interaction. Initially, default synthesis constraints can be used. After that, constraint optimization is mostly done manually, although it can be automated. Most typically, default compile options can be used, although the design engineer may sometimes make manual tweaks. Today, synthesis, layout and STA are typically done by scripts specifically created for each design project.
Sixth, in the ATPG phase, a test sequence is generated. This test sequence is designed in order to test the chip once it has been fabricated (e.g., testing for “stuck-at zero” or “stuck-at one” faults in a CMOS chip). The ATPG phase is another design step that is computationally intensive. As done today, it requires the final net list as input with some small user input file. After the test sequence is executed, an engineer analyzes the output log files to see if any improvements can be made in the design.
The final output of the design process is typically a magnetic tape (“tape-out”) in the GDSII binary format (developed by Cadence Design Systems, Inc. of San Jose, Calif.), which can then be sent by the design engineer to a foundry for actual fabrication of the chip.
The design flow for an integrated circuit is described in more detail in Michael J. S. Smith, “Application Specific Integrated Circuits,” Addison-Wesley, ISBN 0-201-50022-1 (USA 1997), which is incorporated herein by reference in its entirety.
In sum, the six-phase chip design process explained above is complex and time-consuming. While automated tools exist for certain stages of design (e.g., the Design Compiler™ tool, available from Synopsys, Inc. of Mountain View, Calif. for synthesis and the FastScan™ tool, available from Mentor Graphics Corp. of Wilsonville, Oreg. for ATPG), no single integrated tool is currently available to aide engineers at every stage of product design (i.e., from conception to tape-out).
Given the foregoing, what is needed is a system, method and computer program product for a total integrated circuit design tool.
SUMMARY OF THE INVENTION
The present invention, which meets the above-identified need, is a system, method and computer program product for total Web-based integrated circuit design. The present invention allows design engineers to utilize a well-understood graphical interface (i.e., a Web browser) to access a wealth of data and services. The present invention allows designers to evaluate and choose competing standard architectures, and to more efficiently design cores and systems-on-a-chip (SOCs). In essence, the present invention is a “virtual lab” which allows and aides design engineers at every stage of product design. This includes, without limitation, architecture choice, implementation options, software development, and hardware design.
The system of the present invention includes an application database that stores information about users of the system and reference designs for integrated circuits. The system also includes a plurality of servers, each connected to the application database, that possess the code logic necessary to provide the virtual lab functionality described herein while ac
Courtright David A.
Jones Darren M.
Knowles John B.
Lev Lavi A.
MIPS Technologies Inc.
Siek Vuthe
Sterne Kessler Goldstein & Fox P.L.L.C.
LandOfFree
System, method and computer program product for web-based... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System, method and computer program product for web-based..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System, method and computer program product for web-based... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3266441