Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2008-02-26
2011-10-04
Kim, Matt (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S207000, C711SE12014, C711SE12061
Reexamination Certificate
active
08032716
ABSTRACT:
A system, method and computer program product for providing a new quiesce state. The method includes receiving a quiesce request at a system controller from an initiating processor. The quiesce request is sent to a plurality of processors. Notification is received at the system controller that the processors have finished purging their translation look aside buffers (TLBs). A fast quiesce reset command is received at the system controller from the initiating processor once updates to the system resources are complete. It is indicated to the processors that the block translation restriction can be dropped in response to receiving the fast quiesce reset command, thereby allowing the processors to continue processing without block translation restrictions.
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Fee Michael F.
Heller Lisa C.
Jones Christine C.
Campbell John
Cantor & Colburn LLP
International Business Machines - Corporation
Kim Matt
Verderamo, III Ralph A
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