Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2002-01-17
2004-12-14
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S206000
Reexamination Certificate
active
06832304
ABSTRACT:
BACKGROUND
The disclosures herein relate generally to nodes and more particularly to a system, method, and computer program product for mapping a system memory in a multiple node information handling system.
Intel Architecture-32 (IA-32) information handling systems that include more than four gigabytes of physical memory use an addressing mode known as Physical Address Extension (PAE) mode. Some applications and operating systems, however, can require the use of memory that resides below the four gigabyte boundary.
In a multiple processor non-uniform memory architecture (NUMA) system that includes multiple nodes, each node typically includes some local memory. Where a particular node requires memory that is not local to the node, then the node generally expended additional overhead to access the required memory from another node. For example, if a node attempts to execute an operating system or application that requires the use of memory that resides below the four gigabyte boundary and the node does not include local memory below the four gigabyte boundary, then the node may use memory in another node that is below the four gigabyte boundary. This use of the memory of another node may reduce the performance of the system.
Accesses to memory in a system with more than four gigabytes typically require the use of operating system (OS) library extensions. The use of OS library extensions may require additional processing to be performed for these accesses and may reduce the performance of the system. For applications that do not use this memory, the operating system may use the memory beyond four gigabyte boundary for paging.
It would be desirable to be able to map a system memory in a multiple processor system to allow a node to execute as many programs as possible in local memory. Accordingly, what is needed is a system, method, and computer program product for mapping a system memory in a multiple node information handling system.
SUMMARY
One embodiment, accordingly, provides an information handling system for detecting a first memory in a first node and detecting a second memory in a second node coupled to the first node. The system ensures that a first set of contiguous addresses is mapped to a portion of the first memory where the first set of contiguous addresses each have a value lower than a four gigabyte address, and ensures that a second set of contiguous addresses is mapped to a portion of the second memory where the second set of contiguous addresses each have a value lower than the four gigabyte address.
A principal advantage of this embodiment is that various shortcomings of previous techniques are overcome. For example, processing efficiency in a multiple processor node may be increased by ensuring that memories in each node are mapped to include addresses between zero and four gigabytes.
REFERENCES:
patent: 5293631 (1994-03-01), Rau et al.
patent: 5321836 (1994-06-01), Crawford et al.
patent: 5671229 (1997-09-01), Harari et al.
patent: 5682512 (1997-10-01), Tetrick
patent: 5682529 (1997-10-01), Hendry et al.
patent: 5715418 (1998-02-01), Atsatt et al.
patent: 5719808 (1998-02-01), Harari et al.
patent: 5754817 (1998-05-01), Wells et al.
patent: 5819087 (1998-10-01), Le et al.
patent: 5944820 (1999-08-01), Beelitz
patent: 5974517 (1999-10-01), Gaudet
patent: 6029237 (2000-02-01), Beelitz
patent: 6032223 (2000-02-01), Beelitz
patent: 6032239 (2000-02-01), Beelitz
patent: 6041395 (2000-03-01), Beelitz
patent: 6295584 (2001-09-01), DeSota et al.
patent: 6351798 (2002-02-01), Aono
patent: 6701421 (2004-03-01), Elnozahy et al.
Intel Multiprocessor Specification Version 1.4 May 1997.
Rangarajan Madhusudhan
Stultz Paul Dennis
Baker Paul
Dell Products L.P.
Haynes and Boone LLP
Padmanabhan Mano
LandOfFree
System, method and computer program product for mapping... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System, method and computer program product for mapping..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System, method and computer program product for mapping... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3293034