Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2000-09-25
2004-10-12
Sorrell, Eron J (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S035000, C710S052000, C709S235000, C370S360000, C370S415000
Reexamination Certificate
active
06804731
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to data routing systems and, more particularly, to routing packets through a network switch.
BACKGROUND OF THE INVENTION
Ethernet is a widely-installed local area network technology. Specified in a standard, Institute of Electrical and Electronic Engineers (IEEE) 802.3, Ethernet was originally developed by Xerox and then developed further by Xerox, DEC, and Intel. An Ethernet LAN typically uses coaxial cable or special grades of twisted pair wires. A commonly installed Ethernet systems are called 10BASE-T and provide transmission speeds up to 10 Mbps. Devices are connected to the cable and compete for access using a Carrier Sense Multiple Access with Collision Detection (CSMA/CD) protocol. Fast Ethernet or 100BASE-T provides transmission speeds up to 100 megabits per second and may be used for LAN backbone systems, supporting workstations with 10BASE-T cards. Gigabit Ethernet provides an even higher level of backbone support at 1000 megabits per second (1 gigabit or 1 billion bits per second).
Fast Ethernet is a local area network transmission standard that provides a data rate of 100 megabits per second (referred to as “100BASE-T”). Workstations with existing 10 megabit per second (10BASE-T) Ethernet card can be connected to a Fast Ethernet network. (The 100 megabits per second is a shared data rate; input to each workstation is constrained by the 10 Mbps card). Gigabit Ethernet is a local area network transmission standard that provides a data rate of 1 billion bits per second (one gigabit). Gigabit Ethernet is defined in the IEEE 803.2 standard. Gigabit Ethernet may be used as an enterprise backbone. Gigabit Ethernet may be carried on optical fibers (with very short distances possible on copper media). Existing Ethernet LANs with 10 and 100 Mbps cards can feed into a Gigabit Ethernet backbone.
Data may be sent over a packet switching network using digital signals. In a packet switching network, users can share the same paths at the same time and the route a data unit travels can be varied as conditions change. In packet-switching, a message is divided into packets, which are units of a certain number of bytes. The network addresses of the sender and of the destination are added to the packet. Each network point looks at the packet to see where to send it next. Packets in the same message may travel different routes and may not arrive in the same order that they were sent. At the destination, the packets in a message are collected and reassembled into the original message.
Layering is the organization of programming into separate steps that are performed sequentially, defined by specific interface for passing the result of each step to the next program or layer until the overall function, such as the sending or receiving of some amount of information, is completed. Communication programs are often layered. The reference model for communication programs, Open System Interconnection (OSI) is a layered set of protocols in which two programs, one at either end of a communications exchange, use an identical set of layers. OSI includes of seven layers, each reflecting a different function that has to be performed in order for program-to-program communication to take place between computers. Transmission Control Protocol and Internet Protocol (TCP/IP) is an example of a two-layer set of programs that provide transport and network address functions for Internet communication.
A switch is a internetworking device that selects a path or circuit for sending a unit of data to its next destination. A switch may also include the function of a router and determine the route and specifically what adjacent network point the data should be sent to. Relative to the layered Open Systems Interconnection (OSI) communication model, a switch may be associated with the data link layer—Layer 2. Switches may also be capable of performing the routing functions of the network layer—Layer 3. Layer 3 switches are also sometimes called IP switches.
The Data Link Layer of OSI—Layer 2—is concerned with moving data across the physical links in the network. In a network, a switch may be a device that redirects data messages at the Layer 2 level, using the destination Media Access Control (MAC) address to determine where to direct the message. The Data-Link Layer contains two sublayers that are described in the IEEE-802 LAN standards: Media Access Control (MAC), and Logical Link Control (LLC). The Data Link Layer assures that an initial connection has been set up, divides output data into data frames, and handles the acknowledgements from a receiver that the data arrived successfully. It also ensures that incoming data has been received successfully by analyzing bit patterns at special places in the frames.
The Network. Layer of OSI—Layer 3—is concerned with knowing the address of the neighboring nodes in the network, selecting routes and quality of service, and recognizing and forwarding to the transport layer incoming messages for local host domains. A switch may be a Layer 3 device and perform layer 3 functions. The IP address is a layer 3 address.
Switching, does by its nature, involves transient data flows. At Gigabit speeds, these transients occur extremely fast, and in a highly random manner. In the past, it has been difficult to determine in sufficiently fast enough speeds which components of a switch data flows should be directed to so as maximize data flow through the switch and reduce blocking traffic in the switch.
SUMMARY OF THE INVENTION
A system, method and article of manufacture are provided for storing an incoming datagram in a switch matrix of a switch fabric. The switch matrix has a pair of buffers with each buffer having a pair of portions. Data of a datagram is received and the buffer portions are sequentially filled with the data Periodically, transfer of data is allowed from the buffers into the switch matrix. At each period where transfer of data is allowed in the sequence that the buffer portions were filled, the data in one of the buffer portions may be transferred into the switch matrix.
In an aspect of the present invention, data in a buffer portion may only be transferred into the switch matrix if the buffer portion is filled with data or contains an end of a datagram (i.e., the tail or last byte of the datagram). In another aspect of the present invention, the switch matrix may comprise a plurality of memory banks for storing the transferred data. In such an embodiment, the memory banks may alternate in receiving data transferred from the buffer portions.
In a further aspect of the present invention, the buffer portions may each have equal storage capacities for storing received data. In a preferred embodiment, each buffer portion has a storage capacity of 16 bytes for storing the incoming data. In another preferred embodiment, wherein transfer of data may be allowed every 16 cycles.
REFERENCES:
patent: 4639881 (1987-01-01), Zingher
patent: 4998242 (1991-03-01), Upp
patent: 5068916 (1991-11-01), Harrison et al.
patent: 5119370 (1992-06-01), Terry
patent: 5276445 (1994-01-01), Mita et al.
patent: 5408469 (1995-04-01), Opher et al.
patent: 5517495 (1996-05-01), Lund et al.
patent: 5644577 (1997-07-01), Christensen et al.
patent: 5732087 (1998-03-01), Lauer et al.
patent: 5831980 (1998-11-01), Varma et al.
patent: 5835491 (1998-11-01), Davis et al.
patent: 5974518 (1999-10-01), Nogradi
patent: 5982771 (1999-11-01), Caldara et al.
patent: 6016511 (2000-01-01), Cook
patent: 6046979 (2000-04-01), Bauman
patent: 6067300 (2000-05-01), Baumert et al.
patent: 6067301 (2000-05-01), Aatresh
patent: 6078963 (2000-06-01), Civanlar et al.
patent: 6084858 (2000-07-01), Matthews et al.
patent: 6122669 (2000-09-01), Crayford
patent: 6157643 (2000-12-01), Ma
patent: 6163539 (2000-12-01), Alexander et al.
patent: 6185221 (2001-02-01), Aybay
patent: 6252878 (2001-06-01), Locklear, Jr. et al.
patent: 6359861 (2002-03-01), Sui et al.
patent: 6424658 (2002-07-01), Mathur
patent: WO 97/09806 (1997-03-01), None
Chang You-Sung
Chun Jung-Bum
Paion Company, Limited
Sorrell Eron J
Squire Sanders & Dempsey L.L.P.
LandOfFree
System, method and article of manufacture for storing an... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System, method and article of manufacture for storing an..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System, method and article of manufacture for storing an... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3267306