Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral configuration
Reexamination Certificate
2004-05-27
2010-10-05
Park, Ilwoo (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral configuration
C710S038000, C710S316000, C710S317000
Reexamination Certificate
active
07809861
ABSTRACT:
Methods and apparatus are provided optimizing system memory map decoder logic. A system is configured with multiple master and slave components. Using information known about the system configuration, optimized decoder logic can be configured. Critical path delay and system resource usage are reduced by optimizing decoder logic.
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SOC Solutions, SoC-IP1000 Address Decoder, © 2003.
Hutkins Peter
Pritchard Jeffrey Orion
Altera Corporation
Park Ilwoo
Weaver Austin Villeneuve & Sampson LLP
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