System memory map decoder logic

Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral configuration

Reexamination Certificate

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Details

C710S038000, C710S316000, C710S317000

Reexamination Certificate

active

07809861

ABSTRACT:
Methods and apparatus are provided optimizing system memory map decoder logic. A system is configured with multiple master and slave components. Using information known about the system configuration, optimized decoder logic can be configured. Critical path delay and system resource usage are reduced by optimizing decoder logic.

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patent: 5561817 (1996-10-01), McCormack et al.
patent: 5933812 (1999-08-01), Meyer et al.
patent: 7145903 (2006-12-01), Gutierrez
SOC Solutions, SoC-IP1000 Address Decoder, © 2003.

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