Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2000-04-05
2003-09-02
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
C257S758000, C257S776000
Reexamination Certificate
active
06614049
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a system LSI chip having a test structure (test element group: hereinafter abbreviated as TEG) for wires.
2. Description of the Background Art
In a semiconductor device such as an LSI, fining down and layer multiplication of wires progress following fining down and high integration of elements. A wire structure including an interlayer isolation film and a process of manufacturing the same are complicated due to such fining down and layer multiplication of the wires, and it is not too much to say that workmanship of the wires influences the performance and the yield of a product. The workmanship of the wires must be correctly and quickly evaluated for improvement of the yield and process control. Workmanship evaluation of the wires includes various types. For example, there is an evaluation immediately after manufacturing steps for checking whether or not abnormality such as disconnection or shorting is caused by a random factor such as a failure or contamination, whether or not the wires have been formed in a designed width and the like. Another example of evaluation is reliability assessment with an acceleration test for checking aging (occurrence of voids in the wires caused by migration etc.) of a completed chip.
While the workmanship of the wires in the product chip themselves must be evaluated independently of the remaining circuit elements included in the product chip, it is difficult and inefficient to perform such evaluation employing the product chip.
Therefore, the evaluation is generally made employing various TEGs formed with only wire structures. More specifically, the wires are evaluated by measuring a parameter such as the resistance value of such a wire TEG and detecting a portion having deficiency or abnormality by an optical method such as observation with an emission microscope or OBIC (optical beam induced current) analysis when the parameter is different from a designed value.
In general, a test wafer formed with only a wire TEG is manufactured independently of a product wafer, or a wire TEG region is provided on a region of a product wafer excluding a product chip region.
In the former case, however, the test wafer manufactured independently of the product wafer may not correctly reflect abnormality caused in the product wafer by a random factor. Statistical investigation is necessary for improving the detection rate of abnormality caused by a random factor. Consequently, the test wafer must be prepared frequently. However, the cost for the product is disadvantageously increased in this case.
In the latter case, the area occupied by the product chip is reduced due to the wire TEG region provided in the product wafer. Consequently, the yield of the product chip is reduced, to result in increase of the cost for the product. While the area of the wire TEG region may be reduced for avoiding increase of the cost, the detection rate for abnormality caused by a random factor is reduced if the area of the wire TEG region is reduced. Thus, sufficient investigation on the product cannot be expected in this case.
Thus, in the conventional mode of wire TEGs, the cost is inevitably increased in order to improve the detection rate for abnormality caused by a random factor in the product chip.
To this end, it is conceivable to build wire TEGs into the product chip itself. In other words, some free spaces present in the product chip may be utilized as wire TEG forming regions. Japanese Patent Application Laid-Open No. 5-144917 (1993) describes an example of such a technique.
FIG. 9
is a plan view showing a chip CP
2
for illustrating this technique. The chip CP
2
includes free spaces
301
formed with substrate wire TEGs, a region
302
formed with internal cells and normal wires and regions
303
formed with I/O cells.
According to this technique forming the wire TEGs in the product chip, abnormality caused in the product chip by a random factor can be detected without manufacturing a number of test wafers. Further, the free spaces in the product chip are utilized, not to reduce the yield of the product chip. Thus, the workmanship of the wires can be evaluated while avoiding the problems arising in the conventional wire TEGs.
However, Japanese Patent Application Laid-Open No. 5-144917 disclosing this technique describes only that the wire TEGs are formed on the free spaces (four corners of the chip, for example) in the product chip with no consideration on variation of effects with positions for forming the wire TEGs. In the case of the chip CP
2
shown in
FIG. 9
, the wire TEGs are formed in the regions different from the region
302
formed with the internal cells and normal wires and the I/O cell forming regions
303
in plan view. When thus avoiding the regions functioning as the product (hereinafter referred to as product regions) in plan view, however, there is such a possibility that only extremely small free spaces are left and the wire TEG regions cannot have sufficient areas.
A chip having a multilayer wire structure may have a wide free space in addition to a plane provided with a product region. In a system LSI chip integrating a memory part and a logic part, the logic part requires a multilayer wire structure having wires present over a number of layers, while about two upper wire layers necessary for power supply/ground wires may be present in the memory part in general. Therefore, a considerably wide free space, corresponding to the area of the memory part, is present on the upper wire layers of the memory part.
In the system LSI, however, metal films, referred to as dummy patterns, of about several &mgr;m square are generally spread over this free space. The dummy patterns are provided in order not to cause dishing (dish-shaped depressions) on the surface of an interlayer isolation film of the memory part when performing chemical mechanical polishing (hereinafter abbreviated as CMP) for forming wire films of the multi-layer wire structure of the logic part and to attain roughness balance of the metal films for preventing occurrence of etching rate difference between the logic part and the memory part due to small areas of the metal films in the memory part when forming patterns of the wire films of the logic part.
FIGS. 10
to
12
illustrate the structure of such a system LSI chip CP
1
.
FIG. 10
is a plane layout diagram of a memory part MM and a logic part LG on the chip CP
1
, and
FIG. 11
is a plan view showing a region RG on the memory part MM in an enlarged manner for illustrating the arrangement of dummy patterns DP formed in a free space on a memory array. Referring to
FIG. 10
, the memory part MM is designed in a scale substantially identical to that of the logic part LG. While such memory parts MM occupy system LSI chips in various area rates, the memory part MM generally occupies a somewhat large part in the total area of the system LSI chip CP
1
.
FIG. 12
is a sectional view taken along the line C—C in FIG.
11
. As shown in
FIG. 12
, the memory part MM comprises an element layer
402
having a number of memory cells MC (sets of DRAMs and capacitors, for example) on a substrate
401
, while a wire layer
403
having power supply/ground wires IL
1
and IL
2
and a dummy pattern layer
404
formed with a number of dummy patterns DP are provided thereon. The dummy patterns DP have surfaces flush with the surfaces of wires (not shown) of respective layers in a multilayer wire structure of the logic part LG. Referring to
FIG. 12
, the dummy pattern layer
404
includes three layers, for example. Interlayer isolation films IS
0
, IS
1
, IS
2
, IS
3
and IS
4
are formed between the memory cells MC and the power supply/ground wires IL
1
, between the power supply/ground wires IL
1
and the power supply/ground wires IL
2
, between the power supply/ground wires IL
2
and the dummy pattern layer
404
and between the respective layers of the dummy pattern layer
404
respectively for isolating these layers from each other. A passivation film PV protecting
Loke Steven
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Vu Hung Kim
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