System level mechanism for invalidating data stored in the exter

Details System level mechanism for invalidating data stored in the exter System level mechanism for invalidating data stored in the exter

1997-02-12

1998-04-07

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711144, G06F 1300

Patent

active

057377553

ABSTRACT:
A computer system is disclosed including a memory subsystem and a processor subsystem having an external cache and an external mechanism for invalidating cached datablocks in the processor subsystem and for reducing false invalidation operations. The processor subsystem issues a write invalidate message to the memory subsystem that specifies a datablock and that includes an invalidate advisory indication that indicates whether the datablock is present in the external cache. The invalidate advisory indication determines whether the memory subsystem returns an invalidate message to the processor subsystem for the write invalidate operation.

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