System latency levelization for read data

Details System latency levelization for read data System latency levelization for read data

2001-03-13

2003-12-02

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S005000, C711S167000, C711S169000, C711S170000, C365S194000

Reexamination Certificate

active

06658523

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to high speed synchronous memory systems, and more particularly to setting read latencies of memory devices so that read data from any memory device arrives at the memory controller at the same time.
BACKGROUND OF THE INVENTION
An exemplary computer system is illustrated in FIG.
1
. The computer system includes a processor
500
, a memory subsystem
100
, and an expansion bus controller
510
. The memory subsystem
100
and the expansion bus controller
510
are coupled to the processor
500
via a local bus
520
. The expansion bus controller
510
is also coupled to at least one expansion bus
530
, to which various peripheral devices
540
-
542
such as mass storage devices, keyboard, mouse, graphic adapters, and multimedia adapters may be attached.
The memory subsystem
100
includes a memory controller
400
which is coupled to a plurality of memory modules
301
-
302
via a plurality of signal lines
401
a
-
401
d,
402
,
403
,
404
,
405
a
-
405
d.
The plurality of data signal lines
401
a
-
401
d
are used by the memory controller
400
and the memory modules
301
-
302
to exchange data DATA. Addresses ADDR are signaled over an plurality of address signal lines
403
, while commands CMD are signaled over a plurality of command signal lines
402
. The memory modules
301
-
302
include a plurality of memory devices
101
-
108
and a register
201
-
202
. Each memory device
101
-
108
is a high speed synchronous memory device. Although only two memory modules
301
,
302
and associated signal lines
401
a
-
401
d,
402
,
403
,
404
,
405
a
-
405
d
are shown in
FIG. 1
, it should be noted that any number of memory modules can be used.
The plurality of signal lines
401
a
-
401
d,
402
,
403
,
404
,
405
a
-
405
d,
which couple the memory modules
301
,
302
to the memory controller
400
are known as the memory bus
150
. The memory bus
150
may have additional signal lines which are well known in the art, for example chip select lines, which are not illustrated for simplicity. Each row of memory devices
101
-
104
,
105
-
108
which span the memory bus
150
is known as a rank of memory. Generally, single side memory modules, such as the ones illustrated in
FIG. 1
, contain a single rank of memory. However, double sided memory modules containing two ranks of memory may also be employed.
A plurality of data signal lines
401
a
-
401
d
couple the memory devices
101
-
108
to the memory controller
400
. Read data is output serially synchronized to the read clock signal RCLK, which is driven across a plurality of read clock signal lines
405
a
-
405
d.
The read clock signal RCLK is generated by the read clock generator
401
and driven across the memory devices
101
-
108
of the memory modules
302
,
301
, to the memory controller
400
. Commands and addresses are clocked using a command clock signal CCLK which is driven by the memory controller across the registers
201
,
202
of the memory modules
301
,
302
, to a terminator
402
. The command, address, and command clock signal lines
402
-
404
are directly coupled to the registers
201
,
202
of the memory modules
301
,
302
. The registers
201
,
202
buffer these signals before they are distributed to the memory devices
101
-
108
of the memory modules
301
,
302
. The memory subsystem
100
therefore operates under at least a read clock domain governed by the read clock RCLK and a command clock domain governed by the command clock CCLK. The memory subsystem
100
may also have additional clock domains, such as one governed by a write clock (not shown).
When a memory device
101
-
108
accepts a read command, a data associated with that read command is not output on the memory bus
150
until a certain amount of time has elapsed. This time is known as device read latency. A memory device
101
-
108
can be programmed to operate at any one of a plurality of device read latencies, ranging from a minimum device read latency (which varies from device to device) to a maximum latency period.
However, device read latency is only one portion of the read latency seen by the memory controller
400
. This read latency seen by the memory controller, known as system read latency, is the sum of the device read latency and the latency caused by the effect of signal propagation time between the memory devices
101
-
108
and the memory controller
400
. If the signal propagation between each memory device
101
-
108
and the memory controller
400
were identical, then the latency induced by the signal propagation time would be a constant and equally affect each memory device
101
-
108
. However, as
FIG. 1
illustrates, commands CMD, addresses ADDR, and the command clock CCLK are initially routed to registers
201
,
202
before they are distributed to the memory devices
101
-
108
. Each memory device
101
-
104
,
105
-
108
on a memory module
301
,
302
is located at a different distance from the register
201
,
202
. Thus each memory device
101
-
104
will receive a read command issued by the memory controller
400
at different times. Additionally, there are also differences in distance between the memory controller
400
and the registers
201
,
202
of the two memory modules
301
,
302
. Register
201
(on memory module
301
) is closer to the memory controller
400
and will therefore receive commands, addresses, and the command clock before register
202
(on memory module
302
). Thus, every memory device
101
-
108
of the memory subsystem
100
has a different signal path length to the memory controller for its command CMD, address ADDR, and command clock CCLK signals and will receive a read command issued by the memory controller at varying times. At the high clock frequencies (e.g., 300 MHz to at least 533 MHz), these timing differences become significant because they may overlap clock cycle boundaries.
Due to differences in each memory device's
101
-
108
minimum device read latency and differences in their command CMD, address ADDR, and command clock CCLK signal propagation, each memory device
101
-
108
may have a different system read latency. Since each memory device stores only a portion of a memory word, the memory controller normally reads a plurality of memory devices in parallel. The differences in system read latencies among the memory devices
101
-
108
of the memory subsystem
100
makes this task difficult. Accordingly, there is a need for an apparatus and method to equalize the system read latencies of each memory device so that the memory controller can efficiently process a read transaction across multiple memory devices.
SUMMARY OF THE INVENTION
The present invention is directed at a method and apparatus for equalizing the system read latencies of each memory device in a high speed memory system. The equalization process ensures that each memory device responds to the memory controller with the same system read latency, regardless of each device's minimum device read latency and differences in signal propagation time due to differences in the memory device's physical location on the memory bus. Each memory device has a plurality of configuration lines which can be used by the memory controller to set the memory device to operate at any one of a plurality of device read latencies longer than the device's minimum device read latency. During the equalization process, each memory device is initially operated its minimum device read latency. The memory controller reads a calibration pattern to determine each memory device's system read latency. The memory controller calculates an offset which may be added to each memory device's device read latency to cause each memory device to operate at a system read latency equal to the slowest observed system read latency when each memory device is operated at its minimum device read latency. Each memory device is thereafter operated at an increased device latency, with the amount of increase equal to the offset associated with the mem

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