Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2001-12-20
2003-08-12
Ellis, Kevin L. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S147000, C711S154000, C711S158000, C710S117000, C710S241000, C710S244000
Reexamination Certificate
active
06606691
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a system that accommodates agents having different schemes for managing access to a common resource. Typically, the present invention may be applied so as to enable a single system to employ data processors having different techniques for managing access to a common memory. A non-limitative example of such a system is an MPEG codec (coder-decoder implementing the standards defined by the Motion Picture Expert Group).
DESCRIPTION OF THE RELATED ART
Various systems exist in which it is necessary for a common resource to be shared between a plurality of agents, only one of the agents at a time being able to access the shared resource. This is the case, for example, in a data processing device in which several processors share a common memory. In the present document, the term “agent” is used both to designate a module and a process implemented by a module (it being understood that a given module may implement a plurality of processes).
Different schemes have been adopted to manage the accessing of the shared resource by the individual agents. Some systems adopt a time-slotted accessing scheme in which each agent accesses the shared resource at a predetermined instant, for a predetermined period of time, and the agents access the shared resource, repeatedly, in a predetermined order. Other systems adopt a scheme in which agents make access-requests as and when they require access and, in the event that a plurality of requests are issued at the same time, an arbiter decides which access-request will be successful. The arbiter implements an arbitration scheme that is designed to ensure that each agent will have access to the shared resource for a period of time sufficient for its needs. This is usually considered in terms of the “bandwidth” required by each agent.
WO98/12645 describes a method and apparatus for bus arbitration in a system where several devices (central processing unit (CPU), data and instruction caches, image co-processor, etc.) integrated on a microprocessor chip use a shared bus to access a common (synchronous DRAM) memory located off the chip. In this system, there is a weighted allocation of bandwidth to the different agents requiring bus access and the arbiter implements an arbitration scheme that ensures that each device receives the bandwidth allocation it requires.
FIG. 1
illustrates the typical environment of a module designed to use a time-slotted access scheme; in this example the module is a processor, PROC, and the shared resource is a memory, MEM. The module PROC is adapted to access the memory MEM via an interface, INT. Only one module PROC is shown in
FIG. 1
but it is to be understood that, in general, several such modules will be integrated onto a single chip IC
1
. Moreover, although, as illustrated here, the memory interface is provided on-chip, it is to be understood that the present invention is applicable also in the case of re-use of modules designed to be associated with an off-chip memory-interface. The interface INT grants the module PROC access to the memory MEM on the basis of a memory-access scheme according to which predetermined time slots are reserved for the module PROC to transfer data to the memory MEM and/or receive data therefrom.
The interface INT is configurable, that is, the allocation of modules to specific time slots can be changed. A controller CONT applies control data to the interface INT to specify which time slot(s) are to be used for access to memory MEM on behalf of the respective different modules on the chip. The controller CONT also applies control data to the module PROC so as to inform it of the predetermined time slots at which it should fetch data from or write data to the memory MEM (via a buffer internal to the interface INT). The allocation of processing modules to time slots is changed relatively infrequently and, thus, this control data is only sent to the interface and processing modules when a configuration change is required.
In general, each of the processing modules on the chip will repeatedly implement the same processing function, but applied to new data. For example, in the case where the IC
1
of
FIG. 1
is the core of an MPEG encoder, certain pre-set functions are repeatedly performed on successive macro-blocks making up a frame of an image signal, by a group of processing modules. The controller, CONT, internal to IC
1
outputs to the processing modules and the interface synchronization signals (in this example, frame start signals and macro-block start signals) as references for determining when the various predetermined time slots occur. The controller also outputs to the interface address data indicating where in the memory, MEM, data is stored relating to the macro-block or line of pixels to be processed by a given module during a particular time period. This address data will, generally, be defined in terms of a start address, and a number of consecutive address locations to access. In some cases, the address data applicable to a given request to be made by a module depends upon the result of some calculation made by another module (which may be another process of the same physical device). In such a case, the controller receives data regarding the result, from the module performing the calculation and generates address data accordingly.
If the interface INT reads/writes data at a different speed from that used by the module PROC, a buffer, BUF, dedicated to module PROC can be placed between the interface INT and the module PROC, to store the data read from memory, MEM, and intended for this module. In this case, the module PROC is arranged to read/write data from/to the buffer at the predetermined time intervals. In this case, during a read operation, if module PROC does not receive from the buffer an acknowledgement signal indicating that data for it is present in the buffer, operation of this module is stalled until such time a subsequent request is acknowledged.
In the time-slotted memory-access scheme of
FIG. 1
, the module PROC is designed to receive and/or output data during predetermined time periods of set duration, via requests made to the memory interface (or, in some cases, to a buffer) during said predetermined time periods.
FIG. 2
illustrates a typical system including an arbiter arbitrating between different requests issued from a plurality of agents. Once again, in this example, the agents are processing modules PROC′ sharing a common memory, MEM, and only a single agent on the chip, IC
2
, is illustrated in FIG.
2
. In this case, the interface, INT, incorporates an arbiter, ARB, applying an arbitration scheme to determine which of a plurality of access-requests that are valid at a given instant will be successful. The arbitration scheme may be a round-robin scheme, or it may be based upon priorities (perhaps variable priorities) allocated to the different modules, or it may be any other known arbitration scheme. The successful access request is passed to a memory interface MIF which handles the physical access to the memory MEM and the routing of data between MEM and PROC′.
In this system, it is not known beforehand how much time will intervene between the making of a request by a given module and the granting of access by the arbiter in response to the request. Accordingly, for each module a buffer BUF′ is provided between the module and the interface. This intermediate buffer may be implemented using a single memory (SRAM) having separate portions dedicated to different modules.
In the arbitrated memory-access scheme of
FIG. 2
, the modules issue access-requests at variable times and of variable duration, and may receive and/or output data at irregular intervals of variable duration.
In some circumstances it may be desirable to employ in a single system modules that have been designed for different resource-accessing schemes. For example, in the context of an MPEG codec, it can arise that encoder and decoder chips (integrated circuits) are designed separately, the decoder chip making use of
Didier Robin
Miro Sorolla Carolina
Ellis Kevin L.
Gathman Laurie E.
Koninklijke Philips Electronics , N.V.
Song Jasmine
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