Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2000-11-13
2004-10-12
Myers, Paul R. (Department: 2189)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
Reexamination Certificate
active
06804742
ABSTRACT:
BACKGROUND OF THE INVENTION
(1). Field of the Invention
The present invention relates to a system integrated circuit having a data processing system which includes buses and devices. More particularly, the present invention relates to an improvement concerning observation of the internal state of the system integrated circuit.
(2). Description of Related Art
Due to the improvement in the semiconductor processing technique, system LSIs containing a whole data processing system are appearing on the semiconductor market. Typically, a data processing system includes a plurality of devices such as a CPU and a memory, and also includes buses connecting the devices. Conventional data processing systems prior to the appearance of system LSIs are manufactured by housing a plurality of parts (devices) on a board then wiring the board by connecting the parts via buses (such a data processing system is called a board-type system). In contrast, the data processing system in a system LSI is achieved by housing the plurality of devices and buses in an LSI package with high density. Naturally, an electronic equipment containing such a system LSI can be small and light. The data processing system contained in a package is resistant to noises from outside the product containing the package, and therefore provides a stable operation.
Meanwhile, in the board-type system, probes are connected from a logic analyzer to desired points on wires on the board to observe transfers of data or addresses on buses of the data processing system. This, however, is not possible in system LSIs since every bus or connection line is in the system LSIs, namely concealed in the system LSIs. This may cause a problem that when a malfunction occurs in the system, the cause of the malfunction cannot be identified. This will cause the system debugging process to spend a lengthy amount of time.
Designers of system LSIs may try to solve this problem by assigning dedicated output terminals to necessary internal buses. It is typical, however, that the total number of output terminals of system LSIs is strictly restricted to reduce the product size and cost. As a result, assigning output terminals to all of a plurality of 24-bit and 32-bit buses in a system LSI is unrealistic, though possible (for example, when there are three 24-bit buses in a system integrated circuit, 72 output terminals should be assigned to them in total for observation). The output terminals can be assigned to only a limited number of internal buses. This narrows the range of observation in terms of the contents transferred on the buses. In this case, when a malfunction occurs in the system LSI, the cause of the malfunction cannot be thoroughly investigated.
It is expected that as a larger scale of data processing system is housed in the system LSI, the structure of the system LSI becomes complicated and the number of malfunctions occurring in the system LSI increases drastically. This will increase the amount of time spent by the system debugging process since the above-mentioned strict restrictions on the total number of output terminals will remain the same.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a system integrated circuit that identifies the cause of a malfunction even if the number of output terminals of a system LSI to be assigned to the internal buses in the system LSI is strictly restricted.
The above object is fulfilled by a system integrated circuit containing a plurality of buses, comprising: a comparator operable to compare data transferred on one of the plurality of buses with a predetermined expected value; a selector unit operable to output data transferred on one of the plurality of buses to outside the system integrated circuit in accordance with a result of the comparison performed by the comparator.
With the above construction, since the selector unit can change a bus transferring data which is to be output to outside the system integrated circuit, based on whether the comparator judges as “match”, even if the system integrated circuit does not have enough output terminals to be assigned to all of the plurality of buses, observers can recognize, from outside the system integrated circuit, data transferred on various buses in the system integrated circuit.
Since a bus transferring data which is to be output to outside the system integrated circuit is changed based on whether the comparator judges as “match”, when a certain address is suspected of holding some data to cause a malfunction, for example, it is possible for an observer to check from outside the system integrated circuit what kind of data is transferred on a data bus while a location indicated by the suspicious address is
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accessed, by setting the suspicious address in the comparator connected to the address bus and allowing the data transferred on the data bus to be output to the observation bus when the comparator judges as “match”. This enables the observer to observe what kind of data is read or written in the system integrated circuit while there is a high possibility that the malfunction occurs. This enables the observer to detect a cause of the malfunction efficiently.
Furthermore, there may be a case where the cause of a malfunction cannot be detected just by observing data or addresses transferred on buses due to an enormous scale of the data processing system. In such a case, however, the system integrated circuit achieves a high-level observation method of changing observation target buses automatically based on various conditions since in the system integrated circuit, a bus transferring data which should be output to outside the system integrated circuit is changed to another bus each time the comparator judges that an expectation matches data transferred on a bus.
In the above system integrated circuit, each of the plurality of comparators may include a holding unit operable to hold an expected value, and the system integrated circuit further comprises an update unit operable to update an expected value held by each holding unit.
With the above construction, the observer can set the expected value as he/she likes. This makes the detection of the cause of malfunction more efficient.
The above system integrated circuit may further comprise: an output unit operable to output, when the selector unit outputs data transferred on a bus corresponding to the comparator to outside the system integrated circuit, an identification number of the bus to outside the system integrated circuit.
With the above construction, the observer can identify the bus transferring the data that is output to outside the system integrated circuit, where the bus is selected based on whether a comparator detects a match.
In the above system integrated circuit, the plurality of buses may include an external-device-dedicated bus which is used to transfer either a predetermined kind of data or a predetermined address to be output to an external device connected to to the system integrated circuit, and the selector unit continues to output either the predetermined kind of data or the predetermined address to outside the system integrated circuit when the comparator judges that the predetermined expected value does not match the data, and the selector unit outputs data transferred on another bus to outside the system integrated circuit when the comparator judges that the predetermined expected value matches the data transferred on the bus to which the comparator is connected.
With the above construction, an output terminal of the system integrated circuit used for outputting data to an external device can also be used by the selector unit to output data transferred on a bus to outside the system integrated circuit. This improves the cost performance of the system integrated circuit.
The above system integrated circuit may further comprise: a receiving unit operable to receive data from outside the system integrated circuit; and a judgement unit operable to judge whether the data received by the receiving unit either is a default value or includes
Kitamura Tomohiko
Osaka Masataka
Sekibe Tsutomu
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