Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
1998-12-29
2001-10-30
Lee, Thomas (Department: 2782)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S015000, C710S019000, C710S033000, C710S055000, C710S056000, C711S147000, C711S170000
Reexamination Certificate
active
06311237
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an interface device ideal for peripheral devices such as printer devices or the like, a control method, and a printing device using the same.
2. Description of the Related Art
It is well known that parallel interfaces according to the specifications of Centronics (hereafter referred to as “Centronics Interface”) are widely used for transmitting data between a host device such as a personal computer and peripheral devices such as printers or the like. Further, at the present, bidirectional parallel interface standards with upward compatibility with the Centronics Interface have been stipulated by IEEE (IEEE Std. 1284-1994 “Standard Signaling Method for a bi-directional Parallel Peripheral Interface for Personal Computer”; hereafter referred to as “IEEE 1284”).
Bi-directional communication can provide the user with an even more easy-to-use environment, since the state of operation of peripheral equipment such as printer devices and the like can be supervised from the host device. Moreover, not only is ease of use facilitated, but operating panels to notify the state of operation of peripheral equipment or issue work commands can be simplified, thereby providing devices at lower prices.
Now, a configuration example of a printer device having a Centronics Interface is disclosed in Japanese Provisional Patent Publication (KOKAI) No. 8-221250. According to the description in Japanese Provisional Patent Publication (KOKAI) No. 8-221250, the data sent from the host device is temporarily stored in a ring buffer. The data stored in the ring buffer is sequentially read in accompaniment with the printing recording operation of the printer device in the order in which the data has been stored, but in the event that
Transfer speed of the data (reception speed)>Speed at which data is read from ring buffer (1)
holds, data continues to pile up in the ring buffer. In this case, at the point that the remaining available capacity of the ring buffer drops below a certain amount, i.e., when the buffer is full, the printer device asserts a busy signal, so as to suppress any further data transfer from the host device. When the data is further read and the remaining available capacity of the ring buffer recovers to a certain amount, the busy signal is negated, and transmission of data from the host device is resumed.
Also, in the event that an abnormal state occurs, such as depletion of ink or recording paper, the printer device goes off-line, a busy signal is asserted so as to suppress any further data transfer from the host device. The abnormal state is manually corrected by the user, following which the user presses an on-line key, whereby the busy signal is negated, and transmission of data from the host device is resumed.
The above is a description of an arrangement in a compatible mode with a Centronics Interface, i.e., an IEEE 1284 interface, but there is basically no difference in operation in the case of the ECP mode, and transfer of data from the host device is suppressed in the event of a full buffer or an abnormal state (suppression of data transfer when in the ECP mode can be carried out by not executing Event
36
stipulated in IEEE 1284 at the printer device).
On the other hand, as disclosed in Japanese Provisional Patent Publication (KOKAI) No. 9-34596, mainstream arrangements for present-day personal computers involve I/O circuits for keyboards, serial ports, secondary storage devices, etc., to be configured of around one or two chip sets.
Such chip sets for personal computers are commercially available from several semiconductor manufacturers. For example, a chip called PC87303VUL manufactured by USA corporation National Semiconductor bundles circuitry for an IEEE 1284 parallel port, serial port, floppy disk drive controller, IDE hard drive controller, keyboard controller, real-time clock, etc., within a single chip.
Now, it is often the case that the IEEE 1284 parallel port circuit of such a chip set has a FIFO for both transmission and reception. Since this serves for both transmission and reception, the transmission and reception operation cannot be switched from one to another until the FIFO is empty (while switching of the transmission/reception operation may be force-executed, there is no choice in such a case but to clear the data rem-ining in the FIFO).
With an IEEE 1284 interface employed, in the event that there is some sort of abnormal state occurring at the printer device, detailed conditions are notified to the personal computer by means of reverse transfer in ECP mode or by nibble mode. Of course, the IEEE 1284 parallel port circuit in the above chip set executes reception action at this time.
However, abnormal states at the printer occur at completely random timing. Accordingly, in the event that data transfer from the personal computer is immediately suppressed and stopped, data is left within the FIFO in the above chip set without being transferred, so transmission and reception cannot be switched, and consequently notification of the abnormal state cannot be executed.
In the event that there is sufficient available capacity remaining in the ring buffer at the printer device, the FIFO can be emptied by suppressing the data transfer in a somewhat delayed manner, rather than immediately. However, such an arrangement cannot deal at all with occurrences of abnormal states with the buffer full. That is, with the known technique, bidirectional communication may not function properly depending on the circumstances, even if an bi-direction IEEE 1284 interface is employed.
This problem can be fundamentally solved by having independent FIFOs for transmission and reception, instead of one for both transmission and reception. Of course, it is technologically feasible to manufacture chip sets with such a configuration and manufacture personal computers using such chip sets.
However, such means for solving the problem does nothing for the millions of personal computers already on the market and in use.
SUMMARY OF THE INVENTION
The present invention has been made in light of the above problems with the known art, and it is an object thereof to provide an interface device, a control method, and a printing device, whereby bi-directional communication can be made to properly function without making any hardware changes to the personal computer, but rather solely devising an arrangement on the side of the peripheral devices.
In order to achieve the above object, the interface device according to the present invention secures an available capacity area in the reception buffer matching the capacity of the FIFO on the host side, and in the event that data to be sent to the host is generated, data transfer from the host is suppressed. At this time, all the data in the FIFO at the host is transmitted by releasing the aforementioned available area. Thus, the host device can receive the data using the now-empty FIFO.
Further, in the event that the remaining available capacity of the reception buffer drops below a certain value, the reception speed is delayed so as to purchase time for processing the received data. Moreover, in this case, in the event that data to be sent to the host is generated, transfer of data from the host is stopped, and the reception speed is restored to the original speed to quickly transmit the data within the FIFO. The available area secured in the reception buffer is released for reception of this data.
The present invention is configured as follows.
An interface device connected to a host device which sends and receives data via a buffer serving as both a transmission and reception buffer comprises: receiving means for receiving data transmitted by the host device; a reception-buffer for storing received data, the reception buffer to be used according to certain commands and having a stand-by area secured that has capacity equal to or greater than that of the buffer of the host device; and control means for stopping the transmission of data from the host device and
Naito Hisatsugu
Suzuki Noriyuki
Canon Kabushiki Kaisha
Fitzpatrick ,Cella, Harper & Scinto
Lee Thomas
Perveen Rehana
LandOfFree
System including single host buffer for transmit and receive... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System including single host buffer for transmit and receive..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System including single host buffer for transmit and receive... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2561421