Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2008-04-29
2010-06-01
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S027000, C326S021000, C326S086000, C326S087000, C327S108000, C327S112000
Reexamination Certificate
active
07728620
ABSTRACT:
A system including a preemphasis driver circuit and a method. One embodiment includes an output terminal, a main driver coupled between the input terminal and the output terminal and an auxiliary driver coupled to the output terminal, wherein at least one unclocked delay element is coupled between the input terminal and the auxiliary driver.
REFERENCES:
patent: 4829199 (1989-05-01), Prater
patent: 5231319 (1993-07-01), Crafts et al.
patent: 6759868 (2004-07-01), Helt et al.
patent: 6956407 (2005-10-01), Baig et al.
patent: 7155164 (2006-12-01), Savoj
patent: 7183813 (2007-02-01), Kasanyal et al.
patent: 7215144 (2007-05-01), Mitby et al.
patent: 7512193 (2009-03-01), Shing et al.
patent: 2004/0108877 (2004-06-01), Cho et al.
patent: 2007/0075745 (2007-04-01), Song et al.
patent: 2007/0268047 (2007-11-01), Hopkins et al.
Dicke, Billing & Czaja, PLLC
Qimonda AG
Tan Vibol
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