Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2011-07-05
2011-07-05
Bragdon, Reginald G (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S202000, C711S221000, C711SE12014, C711SE12066, C711S141000, C714S006220, C714S006240
Reexamination Certificate
active
07975109
ABSTRACT:
A data processing system includes one or more nodes, each node including a memory sub-system. The sub-system includes a fine-grained, memory, and a less-fine-grained (e.g., page-based) memory. The fine-grained memory optionally serves as a cache and/or as a write buffer for the page-based memory. Software executing on the system uses a node address space which enables access to the page-based memories of all nodes. Each node optionally provides ACID memory properties for at least a portion of the space. In at least a portion of the space, memory elements are mapped to locations in the page-based memory. In various embodiments, some of the elements are compressed, the compressed elements are packed into pages, the pages are written into available locations in the page-based memory, and a map maintains an association between the some of the elements and the locations.
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Bodwin James M.
Bruening Ulrich
Cohen Earl T.
McWilliams Thomas M.
Bragdon Reginald G
Faal Baboucarr
Schooner Information Technology, Inc.
SNR Denton US LLP
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