Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1995-12-04
1998-10-06
Lee, Thomas C.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
395875, 711 3, 711119, 711124, 711143, 711146, G06F 1300, G06F 1316
Patent
active
058191054
ABSTRACT:
A memory controller provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When a PCI device executes a memory read, the processor cache and L2 cache are snooped in parallel with the memory read operation. Data is not provided until the snoop operation is complete. If the snoop operation indicates a modified location, a writeback operation is performed before data is provided to the PCI bus. If data is coherent between the memory and caches, data is provided from the memory to the PCI bus.
REFERENCES:
patent: 4926317 (1990-05-01), Wallach et al.
patent: 5072369 (1991-12-01), Theus et al.
patent: 5119485 (1992-06-01), Ledbetter, Jr. et al.
patent: 5228134 (1993-07-01), MacWilliams et al.
patent: 5293603 (1994-03-01), MacWilliams
patent: 5325508 (1994-06-01), Parks et al.
patent: 5341487 (1994-08-01), Derwin et al.
patent: 5353415 (1994-10-01), Wolford et al.
patent: 5369753 (1994-11-01), Tipley
patent: 5426765 (1995-06-01), Stevens et al.
patent: 5446863 (1995-08-01), Stevens et al.
patent: 5469558 (1995-11-01), Lieberman et al.
patent: 5488709 (1996-01-01), Chan
patent: 5524233 (1996-06-01), Milburn et al.
patent: 5524234 (1996-06-01), Martinez, Jr. et al.
patent: 5611071 (1997-03-01), Martinez, Jr.
Thorson, Mark, Second-level cache coherency pit falls: two-level cache designs create complex System-level problems, Microprocessor Report, pp.11-14, Mar. 1990.
Collins Michael J.
Larson John E.
Moriarty Michael P.
Thome Gary W.
Compaq Computer Corporation
Kim Ki S.
Lee Thomas C.
LandOfFree
System in which processor interface snoops first and second leve does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with System in which processor interface snoops first and second leve, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System in which processor interface snoops first and second leve will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-91975