System having read-modify-write unit

Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique

Reexamination Certificate

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C710S310000

Reexamination Certificate

active

06959367

ABSTRACT:
A data processing system incorporates a central processing unit to decode and execute given instructions; a memory to store given data; a bus interface unit, provided between the central processing unit and the memory, to start a read bus cycle to read data from the memory, a write bus cycle to write data to the memory, or a dummy bus cycle different from the read and write bus cycles; and a read-modify-write unit provided between the central processing unit and the bus interface unit. The read-modify-write unit includes a modify-requirements buffer to store modify requirements having modify data output from the central processing unit and an operation control signal; and a modify operation circuit to apply an operation processing to read data output from the bus interface unit with the modify data output from the modify-requirements buffer under the operation control signal to output an operation result to the bus interface unit, as write data.

REFERENCES:
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patent: 5666515 (1997-09-01), White et al.
patent: 6226017 (2001-05-01), Goossen et al.
patent: 6405276 (2002-06-01), Chen et al.
patent: 6745302 (2004-06-01), Taniguchi et al.
patent: 6795901 (2004-09-01), Florek et al.
patent: 3-48370 (1991-03-01), None
patent: 5-81122 (1993-04-01), None
patent: 9-54694 (1997-02-01), None
patent: 2001-75826 (2001-03-01), None
C. P. Freeman, IBM Technical Disclosure Bulletin, vol. 27, No. 8, XP-000714709, pp. 5019-5020, “Read-Modify-Write Data Integrity”, Jan. 1985.

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