System having processor monitoring capability of an integrated c

Details System having processor monitoring capability of an integrated c System having processor monitoring capability of an integrated c

1998-01-27

2000-06-06

Ray, Gopal C.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710126, 710100, G06F 1300, H05K 100, H01L 2500

Patent

active

060732008

ABSTRACT:
A system is delineated comprising, in combination, an integrated circuit having N internal masters coupled to a buried, internal bus, and register circuitry coupled to the buried, internal bus and having an output providing status data for each of the N internal masters. The output from the register circuitry is directly coupled to a processor for permitting the processor to monitor request and grant status for each internal master, thereby allowing the processor to keep track of which, if any, of the internal masters attempt to "hog" the internal, buried bus. Additionally, the processor can set enabling registers located in the register circuitry to one value for permitting properly operating internal masters to have access to the internal, buried bus, and to another value to disable one or more "hogging" internal masters from accessing the internal, buried bus. The system further includes N external devices coupled, on a one-to-one basis, to the N internal masters.

REFERENCES:
patent: 4099236 (1978-07-01), Goodman et al.
patent: 5017993 (1991-05-01), Shibata
patent: 5784291 (1998-07-01), Chen et al.
patent: 5794014 (1998-08-01), Shetty et al.
patent: 5809259 (1998-09-01), Mitsuishi
patent: 5857094 (1999-01-01), Nemirovsky

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