Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2002-10-11
2004-06-08
Huynh, Kim (Department: 2182)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S309000, C710S308000, C710S022000, C709S250000
Reexamination Certificate
active
06748479
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to the fields of packet processing and coherency.
2. Description of the Related Art
With the continued expansion of networks and networked systems (e.g. local area networks (LANs), wide area networks (WANs), the Internet, etc.), packet processing is an increasingly important function for a variety of systems. The amount of packet processing to be performed may be increasing due to the increased amount of packet traffic, as well as the more sophisticated packet processing that is being attempted on each packet (e.g. processing at deeper layers of the packet).
A packet processing system must therefore be capable of receiving packets for processing and transmitting processed packets (or newly generated packets). Additionally, it may be desirable for a packet processing systems to be scalable, so that the packet processing system may be expanded to handle increased packet processing responsibilities.
SUMMARY OF THE INVENTION
In one embodiment, an apparatus includes one or more interface circuits, an interconnect, a memory controller coupled to the interconnect, a memory bridge coupled to the interconnect, a packet direct memory access (DMA) circuit coupled to the interconnect, and a switch. Each interface circuit is coupled to a respective interface. The one or more interface circuits are coupled to receive packets and coherency commands from the interfaces. The memory controller is configured to couple to a memory. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in the memory. In some embodiments, the apparatus may provide scalability through the coherency and routing of packet traffic among multiple instances of the apparatus.
A method is contemplated. Packets and coherency commands are received on one or more interfaces. The packets and the coherency commands are routed through a switch, wherein the packets are routed to a packet DMA circuit and the coherency commands are routed to a memory bridge. The memory bridge generates transactions on an interconnect in response to at least some of the coherency commands. The packet DMA circuit generates transactions on the interconnect to write the packets to a memory.
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Gulati Manu
Keller James B.
Moll Laurent R.
Oner Koray
Rowlands Joseph B.
Broadcom Corporation
Huynh Kim
Merkel Lawrence J.
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