System having a plurality of frame bytes capable of identifying

Details System having a plurality of frame bytes capable of identifying System having a plurality of frame bytes capable of identifying

1995-11-30

1999-03-09

An, Meng-Ai T.

395309, 395877, 39520062, 39520064, 39520065, 39520066, G06F 1300

Patent

active

058812474

ABSTRACT:
A bus structure for interconnecting the modules of an industrial automation controller includes DATA lines and associated control lines that enable interface circuits on each module to transfer frames of data. The interface circuit includes a flow control circuit for managing resources within the receiving module, and thus controlling the flow of data over the backplane bus. As soon as a message begins to be received, the flow control circuit makes a determination as to the availability of resources within the module to successfully receive the data frame. If sufficient resources are not available, a busy indication is returned to the transmitting module, and the transmitting module then aborts the transmission. The factors evaluated by the interface circuit in forming the determination as to the availability of resources includes the factors of: (a) availability of a control block when the frame begins a new complete message, (b) completion of processing for a frame from a particular source module before accepting another frame from that module, and (c) availability of a buffer for receiving the frame.

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IEEE Standard for Futurebus+ -Logical Protocol Specification, IEEE Computer Society, Sep. 26, 1991, pp. 39 to 56. Multibus II Bus Architecture Specification, Intel Corporation, 1984, pp. 2-27 to 2-37.

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