Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
1999-02-10
2002-07-02
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S005000, C710S025000, C710S026000, C711S171000
Reexamination Certificate
active
06415338
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to computer systems, and more particularly to a direct memory access (DMA) controller.
BACKGROUND OF THE INVENTION
As is well known, DMA transfers involve the movement or transfer of data from one memory device to another memory device (within a computing system) across a system bus, and without intervening communication through a processor.
More particularly, a processor such as a CPU typically controls and coordinates the execution of instructions within computing system. Ancillary to this operation, the CPU must frequently move data from a memory or other peripheral device into the CPU for processing, or out of the CPU to a memory or other peripheral device after processing. The CPU also often coordinates the movement of data from one memory or peripheral device to another memory or peripheral device.
In very early computing systems, this latter movement of data was accomplished by first reading the data directly from one memory device into the processor, then immediately writing that same data out to another memory device. As computing systems advanced, DMA controllers were created to facilitate such data transfers by controlling the movement of data directly from one memory device to another memory device.
FIG. 1
shows a block diagram illustrating certain fundamental components of a computer system that are utilized in connection with such a conventional DMA transfer. In this regard, a single DMA controller
10
is illustrated in connection with a source memory
12
, a destination memory
14
and a CPU or some other processing circuit
16
. Each of the devices is illustrated as being interconnected, or otherwise disposed for intercommunication, via a bus
18
, which preferably comprises both address and data lines. The devices are also interconnected through various control and other signaling lines
19
,
20
,
21
, and
22
. In operation, data
24
may be directly transferred between memory devices
12
and
14
across the bus
18
, without having to transition through the CPU
16
, which allows data to be transferred between the memories at a much higher rate.
As is known, there are three primary steps involved in a DMA transfer. First, the processor
16
sets up the DMA transfer by supplying a DMA controller
10
with the identity of the source and destination memories
12
and
14
, the address of the first bit to byte to be transferred from the source memory
12
, as well as the number of bytes to be transferred. Once the CPU
16
has communicated this information to the DMA controller
10
, the DMA controller
10
starts the operation by either taking control of the bus
18
, or otherwise requesting shared control of the bus with other devices (not shown). In this regard, other devices that are disposed along the same bus
18
may share the bus, the allocation of which may be controlled by an arbitration circuit (not shown), as is understood by those skilled in the art. Once the DMA controller
10
has the bus
18
, it initiates the bus transfer (assuming that the data is available for transfer). In this regard, and as will be understood by persons skilled in the art, if the data were temporarily stored within a cache memory, or some other device (not shown), then the data actually stored in the memory device
12
, would be considered “dirty data”, and therefore not subject to transfer. Resolution of nuances such as this are known by those skilled in the art, and need not be discussed herein, in order to effectively illustrate the basic DMA operations as are known by prior art systems,
Utilizing control lines
21
and
22
, the DMA controller
10
may orchestrate the transfer of data from the source memory
12
to the destination memory
14
. The DMA controller
10
may control the address supplied on address bus
18
, as well as the chip select and enable lines necessary in order to read data from a select memory address of the source memory
12
and write that same data to a select memory address in the destination memory
14
. Assuming that a plurality of data bytes are to be transferred from the source memory
12
to the destination memory
14
, then the DMA control
10
will update the addresses on bus
18
accordingly. Once the DMA transfer is complete, the DMA controller
10
may interrupt the CPU
16
to inform it accordingly. It will be appreciated that throughout the duration of the DMA transfer, the CPU
16
may be performing various processing operations. As is known, this greatly enhances the overall efficiency of the system by allowing the CPU
16
to perform processing tasks, without having to get bogged down in managing simple data transfers between memory devices.
Notwithstanding the various advantages and efficiency gains achieved by DMA devices, there is a constant desire to improve on performance. One manner in which performance improvements have been obtained is through the use of DMA controllers that include the ability to execute commands. In such devices, as the DMA controller operates, it may program itself with a self-executing command and start a DMA cycle according to the command.
It has been found, however, that the instruction sets of DMA controllers known in the prior art are relatively constrained. There is, therefore, a need for a DMA controller that provides an enhanced instructions set.
SUMMARY OF THE INVENTION
Certain objects, advantages and novel features of the invention will be set forth in part in the description that follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
To achieve the foregoing and other objects, the present invention is directed to an improved direct memory access (DMA) controller for executing commands having an improved instruction set. In accordance with one aspect of the present invention, a DMA controller is provided having an enhance command set. Specifically, a DMA controller is provided having the ability to perform a memory fill command.
Thus, in accordance with one aspect of the invention, a method is provided for controlling a DMA controller to execute a memory fill command, wherein the method obtains a starting address, a segment length identifier, and a data value. Preferably, this information is obtained by reading successive bytes from external memory. The method then writes the data value to a plurality of consecutive locations in the memory, beginning at the starting address, wherein the number of consecutive locations written to is equal to the segment length identifier.
In accordance with another aspect of the invention, a method is provided for controlling a DMA controller to execute a memory fill command, wherein the method obtains a starting address, an ending address, and a data value. As described above, this information is preferably obtained by reading successive bytes from external memory. The method then writes the data value to a plurality of consecutive locations in the memory, beginning at the starting address and ending at the ending address.
Other features and advantages of the present invention will become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional features and advantages be included herein within the scope of the present invention, as is defined in the claims.
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Elamin Abdelmoniem
Globespan, Inc.
Lee Thomas
Thomas Kayden Horstemeyer & Risley
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