System for validating and monitoring semiconductor testing...

Details System for validating and monitoring semiconductor testing... System for validating and monitoring semiconductor testing...

2001-09-12

2004-04-20

Zarneke, David A. (Department: 2829)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S1540PB

Reexamination Certificate

active

06724211

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a system for validating and monitoring semiconductor testing tools, particularly to a validating and monitoring system which validates a setup condition and monitors performance of a testing tool for integrated circuit testing.
2. Description of the Prior Art
Validation of a testing tool is needed before the tool released to mass production. Monitoring of the tool is also needed during mass production. The validation and monitoring of the testing tool help to avoid wrong testing results of wafers and to do some corrections in time when an error occurs.
For example, the setup condition of a prober/tester is validated using a sample wafer before released to mass production. The sample wafer has been tested to derive original test results. The original test results are validated before the sample wafer is used to validating the testing tool. The prober/tester to be validated tests the sample wafer and derives another group of test results. A comparison of the original test results with those from the prober/tester determines if the setup condition of the prober/tester must be corrected.
The expensive sample wafer must be re-used for the sake of cost. Therefore, the number of times which each die on the sample wafer is tested for setup condition validation is recorded since there is a life time limitation for each die. The dices out of their life times are not used anymore.
There is also a selection rule of the dices for each kind of products to be tested. An operator of the setup condition validation selects the dices to be tested among those within their life times according to the rule.
Besides, the prober/tester is monitored during mass production. Some actions for correction are needed when an error occurs. For example, the testing is stopped or re-done when three or more test results in success are the same, failed or any one of the test results is not reasonable.
Conventionally, the previously described validation and monitoring are manually operated. The operator must record the numbers of times which the dices are tested, select the dices, compare the test results and decide an action according to the comparison results. However, manual operation causes mistakes easily.
SUMMARY OF THE INVENTION
Therefore, the object of the present invention is to provide a system for validating and monitoring semiconductor testing tools, wherein the validation and monitoring are automatically implemented.
The present invention provides a system for monitoring semiconductor testing tools comprising a tester testing a semiconductor device, whereby a test result is derived, a storage device storing a logic function corresponding to the semiconductor device, and a processor receiving the test result and the logic function from the tester and storage device respectively, and applying the logic function to the test result for validation.
The present invention further provides a system for validating semiconductor test tools using a semiconductor device which a first test result has been derived from and validated, the system comprising a tester testing the semiconductor device, whereby a second test result is derived, a storage device storing the first test result of the semiconductor device, and a processor receiving the first and second test result from the storage device and tester respectively, and comparing the first and second test result for validation of the second test result.


REFERENCES:
patent: 5654632 (1997-08-01), Ohno
patent: 5861660 (1999-01-01), McClure
patent: 6037793 (2000-03-01), Miyazawa et al.
patent: 6097204 (2000-08-01), Tanaka et al.
patent: 6246971 (2001-06-01), Kermani et al.

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