Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2011-01-11
2011-01-11
Lin, Sun J (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07870531
ABSTRACT:
A mask reuse methodology process in which the soft logic is implemented with a generic array type cell structure mask and a custom blocking mask. A system is provided comprising a mask set having a plurality of reusable masks corresponding to a plurality of hard intellectual property (IP) components; a generic array type cell mask; and a custom blocking mask that includes blocking regions that positionally correspond with a set of IP components printed on a die.
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patent: 6383847 (2002-05-01), Ditlow et al.
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patent: 6976197 (2005-12-01), Faust et al.
patent: 7176716 (2007-02-01), Madurawe
Bhattacharya Subhrajit
Darringer John
Ostapko Daniel L.
Hoffman Warnick LLC
International Business Machines - Corporation
Lin Sun J
Verminski Brian
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