System for using a cache memory with a write-back architecture

Details System for using a cache memory with a write-back architecture System for using a cache memory with a write-back architecture

1997-04-02

1999-05-04

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711141, 711143, 711146, G06F 1200

Patent

active

059000163

ABSTRACT:
A computer system includes a microprocessor, a cache memory, main memory and supporting logic. The supporting logic includes cache control logic that determines whether an access to memory results in a hit to the cache for dirty or clean data. When a write to the cache results in a hit to clean data, the bus cycle is enlarged in order to set a dirty bit associated with the write data. The bus cycle is enlarged by requesting the processor to refrain from commencing a new bus cycle or driving a new memory address.

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