Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
1999-11-29
2004-01-06
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S300000, C713S320000, C713S323000, C713S340000
Reexamination Certificate
active
06675304
ABSTRACT:
BACKGROUND
This invention relates generally to processor-based systems and particularly to the control of voltage regulators in those systems.
Different types of power and thermal management techniques have been implemented in processor-based systems. One technique, defined in the Advanced Configuration and Power Interface (ACPI) Specification, rev. 1.0, published on Dec. 22, 1996, provides an interface between the operating system of a processor-based system and hardware devices to implement power and thermal management.
The ACPI specification describes a number of processor states each with different power consumption. As a processor transitions to ever lower power consumption states, the time for the processor to return to a full performance state may be reduced. In connection with some of these transitions, the output voltage of a voltage regulator for the processor-based system changes from a higher to a lower output level.
In the ACPI specification, a processor may include a plurality of low activity states such as the C
1
, C
2
or C
3
states. In the deep sleep state, which may be the C
3
state defined under the ACPI specification, the external clock to the processor is disabled so that no activities are performed by the processor except maintenance of the stored data in the processor's internal caches. In the stop grant or C
2
state, the processor performs minimal activity, such as snooping for an internal cache line to maintain cache coherency. While the processor is in the lower activity state, the performance mode of the processor may be changed by, for example, changing the core clock frequency and adjusting the core voltage level.
Thus, the processor may operate in multiple states (or speeds) and may transition automatically between these states. In conjunction with these transitions, the operating voltage of the processor is sometimes changed. Normally, the operating, or core voltage supply is heavily filtered with large bulk capacitors as well as high frequency decoupling capacitors.
The transition between states or speeds of the processor-based system is normally performed when the processor is in a lower power consumption state. This means that the current load on the voltage supply is quite low. When transitioning from a higher to a lower voltage, the bulk capacitors discharge to allow the supply to settle to the required voltage. Since the load is low, this transition can take a relatively long time, increasing the transition latency.
Thus there is a need to improve the latency of voltage regulator output level transitions.
SUMMARY
In accordance with one aspect, a method includes transitioning a processor from a higher to a lower activity state. The load on the voltage regulator is increased at a time when the processor is in the lower activity state.
Other aspects are set forth in the accompanying detailed description and claims.
dr
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1
is a block diagram of a processor-based system in accordance with one embodiment of the present invention;
FIG. 2
is a block diagram of power management control logic in the system of
FIG. 1
in accordance with one embodiment of the present invention;
FIGS. 3 and 4
are timing diagrams that show signal events in the performance of a voltage regulator output voltage reduction in the case of FIG.
3
and an output voltage increase in the case in
FIG. 4
; and
FIG. 5
is a flowchart for software in accordance with one embodiment of the present invention.
REFERENCES:
patent: 4686617 (1987-08-01), Colton
patent: 4945444 (1990-07-01), Schwertlein et al.
patent: 5079448 (1992-01-01), Matsumoto
patent: 5594636 (1997-01-01), Schauder
patent: 6006336 (1999-12-01), Watts et al.
patent: 6232830 (2001-05-01), Fournel
patent: 6266776 (2001-07-01), Sakai
patent: 6278598 (2001-08-01), Suzuki et al.
patent: 6522981 (2003-02-01), Smit et al.
patent: 04225615 (1992-08-01), None
Rius, J.; Figueras, J.; “Detecting IDDQ Defective CMOS Circuit by Depowering ”, VLSI Test Symposium, 1995. Proceedings., 13th IEEE, Apr. 30-May 3, 1995, Page(s): 324-329.
Pole, II Edwin J.
Rushford Scott R.
Intel Corporation
Lee Thomas
Trujillo James K
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