Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-05-24
2004-02-17
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C370S257000, C370S345000, C370S410000
Reexamination Certificate
active
06694488
ABSTRACT:
I. DESCRIPTION OF THE INVENTION
I.A. Field of the Invention
This disclosure teaches a methodology for the design of custom system-on-chip communication architecture. Specifically a novel electronic system and a method of designing a communication architecture are disclosed. This Application is concurrently filed with U.S Patent Application No. 09/576,956 by Raghunathan et, al.
I.B. Background of the Invention
The evolution of the System-on-Chip (SOC) paradigm in electronic system design has the potential to offer the designer several benefits, including improvements in system cost, size, performance, power dissipation, and design turn-around-time. The ability to realize this potential depends on how well the designer exploits the customizability offered by the system-on-chip approach. While one dimension of this customizability is manifested in the diversity and configurability of the components that are used to compose the system (e.g., processor and domain-specific cores, peripherals, etc.), another, equally important, aspect is the customizability of the system communication architecture. In order to support the increasing diversity and volume of on-chip communication requirements, while meeting stringent performance constraints and power budgets, communication architectures need to be customized to the target system or application domain in which they are used.
I.B.1. Related Work
Related work in the fields of system-level design, HW/SW co-design, and networking protocols, have been examined herein to place the disclosed techniques in the context of conventional technologies. A substantial body of work exists in relation to system-level synthesis of application-specific architectures through HW/SW partitioning and mapping of the application tasks onto pre-designed cores and application-specific hardware. For more details, see D. D. Gajski, F Vahid, S. Narayan and J. Gong,
Specification and Design of Embedded Systems
. Prentice Hall, 1994; G. De Micheli,
Synthesis and Optimization Digital Circuits
. McGraw-Hill, New York, N.Y., 1994; R. Ernst, J. Henkel, and T. Benner, “Hardware-software cosynthesis for microcontrollers,” IEEE Design & Test Magazine, pp.64-75, Dec. 1993; T. B. Ismail, M. Abid, and M. Jerraya, “COSMOS: A codesign approach for a communicating system,” in Proc. IEEE International Workshop on Software/Codesign, pp. 17-24, 1994; A. Kalavade and E. Lee, “A globally critical/locally phase driven algorithm for the constrained hardware software partitioning problem in Proc. IEEE
International Workshop on Hardware/Sotware Codesign
, pp. 42-48, 1994; P. H. Chou, R. B. Ortega, and G. B. Borriello, ‘The CHINOOK hardware/software cosynthesis system,” in Proc. Int. Symp. System Level Synthesis, pp. 22-27, 1995; B. Lin, “A system design methodology for software/hardware codevelopment of telecommunication network applications,” in
Proc. Design Automation Conf
, pp. 672-677, 1996; B. P. Dave, G. Lakshminarayana, and N. K. Jha, “COSYN: hardware-software cosynthesis of embedded systems,” in
Proc. Design Automation Conf
, pp. 703-708, 1997 and P. Knudsen and J. Madsen, “Integrating communication protocol selection with partitioning in hardware/software codesign,” in
Proc. Int. Symp. System Level Synthesis
, pp. 111-116, Dec. 1998.
While some of these conventional techniques attempt to consider the impact of communication effects during HW/SW partitioning and mapping, they either assume a fixed communication protocol (e.g., PCI-based buses), or select from a “communication library” of a few alternative protocols. Research on system-level synthesis of communication architectures mostly deals with synthesis of the communication architecture topology, which refers to the manner in which components are structurally connected through dedicated links or shared communication channels (buses). For more details on these architectures, see T. Yen and W. Wolf, “Communication synthesis for distributed embedded systems,” in
Proc. Int. Conf. Computer-Aided Design
, pp. 288-294, Nov. 1995; J. Daveau, T. B. Ismail, and A. A. Jerraya, “Synthesis of system-level communication by an allocation based approach,” in
Proc. Int. Symp. System Level Synthesis
, pp. 150-155, Sept. 1995; M. Gasteier and M. Glesner, “Bus-based communication synthesis on system level,” in ACM
Trans. Design Automation Electronic Systems
, pp. 1-11, Jan. 1999 and R. B. Ortega and G. Borriello, “Communication synthesis for distributed embedded systems,” in
Proc. Int. Conf. Computer-Aided Design
, pp. 437-444, 1998.
While topology selection is a critical step in communication architecture design, equally important is the design of the protocols used by the channels/buses in the selected topology. For example, the nature of communication traffic generated by the system components may favor the use of a time-slice based bus protocol in some cases, and a static priority based protocol in others. For more details, see “Sonics Integration Architecture, Sonics Inc. (http://www.sonicsinc.com/).” and
On-Chip Bus Development Working Group Specification I Version
1.1.0. VSI Alliance, Aug. 1998. The VSI Alliance on-chip bus working group has recognized that a multitude of bus protocols will be needed to serve the wide range of SOC communication requirements. See
On-Chip Bus Development Working Group Specification I Version
1.1.0. VSI Alliance, Aug. 1998. Further, most protocols offer the designer avenues for customization in the form of parameters such as arbitration priorities, transfer block sizes, etc. Choosing appropriate values for these parameters can significantly impact the latency and transfer bandwidth associated with inter-component communication.
Finally, there is a body of work on interface synthesis, which deals with automatically generating efficient hardware a implementations for component-to-bus or component-to-component interfaces. For more details, see G. Borriello and R. H. Katz, “Synthesis and optimization of interface transducer logic,” in
Proc. Int. Conf Computer Design
, Nov. 1987; J. S. Sun and R. W. Brodersen, “Design of system interface modules,” in
Proc. Int. Conf. Computer-Aided Design
, pp. 478-481, Nov. 1992; P. GutberIet and W. Rosenstiel, “Specification of interface components for synchronous data paths,” in
Proc. Int. Symp. System Level Synthesis
, pp. 134-139, 1994; S. Narayanan and D. D. Gajski, “Interfacing incompatible protocols using interface process generation,” in
Proc. Design Automation Conf
., pp. 468-473, June 1995; P. Chou, R. B. Ortega, and O. Borriello, “Interface co-synthesis techniques for embedded systems,” in
Proc. Int. Conf. Computer-Aided Design
, pp. 280-287, Nov. 1995; J. Oberg, A. Kumar, and A. Hemani, “Grammar-based hardware synthesis of data communication protocols,” in
Proc. Int. Symp. System Level Synthesis
, pp. 14-19, 1996; R. Passerone, J. A. Rowson, and A. Sangiovanni-Vincentelli, “Automatic synthesis of interfaces between incompatible protocols,” in
Proc. Design Automation Conf
., pp. 8-13, June 1998 and J. Smith and G. De Micheli, “Automated composition of hardware components,”
in Proc. Design Automation Conf
., pp. 14-19, June 1998. These techniques address issues in the implementation of specified protocols, and not in the customization of the protocols themselves.
In summary, conventional technologies in the field of system-level design and HW/SW co-design do not adequately address the problem of customizing the protocols used in SOC communication architectures to the needs of the application. Further, in previous research, design of the communication architecture is performed statically using information about the application and its environment (e.g., typical input traces). However, in several applications, the communication bandwidth required by each component, the amount of data it needs to communicate, and the relative “importance” of each communication request, may be subject to significant dynamic variations. In such situations, protocols used in conventional communication architectures may not be capable of adapting the underlying communica
Lahiri Kanishka
Lakshminarayana Ganesh
Raghunathan Anand
NEC Corporation
Rossoshek Yelena
Siek Vuthe
Sughrue & Mion, PLLC
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