Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-03-29
2002-05-07
Ray, Gopal C. (Department: 2181)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S715000
Reexamination Certificate
active
06385738
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to testing of data communication networking devices, more particularly to a transceiver employed in an Ethernet type network.
2. Background Art
Device testing plays a critical role in the manufacturing of networking equipment. Manufacturers are continually seeking ways to produce this equipment more economically. One way of accomplishing this is to reduce testing costs. Because of the prevalence of local area networks, a small cost reduction measure translates into a competitive edge in the marketplace.
Local area networks use a network cable or other network media to link nodes (e.g., workstations, routers and switches) to the network. Each local area network architecture uses a media access control (MAC) enabling network interface device at each network node to share access to the media. Physical (PHY) layer devices are configured for translating digital packet data received from a MAC across a standardized interface, e.g., a Media Independent Interface (MII), into an analog signal for transmission on the network medium, and reception of analog signals transmitted from a remote node via the network medium. An example is the 100Base-TX Ethernet (IEEE Standard 802.3u) transceiver, which is configured for transmitting and receiving a Multi-level Transmission-3 (MLT-3) encoded analog signal over unshielded (or shielded) twisted pair copper wiring. To transmit an MLT-3 encoded signal across the media, 4-bit codes from the MII are supplied to a 4B/5B (4 bit/5 bit) encoder. The newly generated 5-bit symbols are serialized and outputted onto the physical media as MLT-3 encoded signals at 125 Mbps. The physical channel rate of 125 Mbps results from use of a 25 MHz internal clock that is multiplied by 5. At the receive end, the physical channel rate of 125 Mbps is effectively reduced to a 100 Mbps physical layer interface because the received 5-bit symbols are decoded back into 4-bit MII codes (i.e., nibbles). Although the physical channel rate is 125 MHz, the MII utilizes a 25 MHz clock. To maintain the 125 MHz rate, a digital phase-locked loop (PLL) recovers the clock information, and a deserializer performs a serial to parallel conversion in which one serial bit translates to 5 outgoing parallel bits at 25 MHz.
In testing the transmitter logic of a PHY device, determining the proper polarity of the encoded signals poses a problem. On the transmit side of the PHY device, a phase-locked loop (PLL) multiplies the 25 MHz clock up to 125 MHz. At power up or reset, the PLL requires a period of time to calibrate itself. The number of 125 MHz clock cycles that are generated until calibration of the PLL is not determinable. That is, the number of transitions that occur during the period of calibration is unknown, despite the fact that the PHY device is the source of the transmission. Factors that contribute to the non-deterministic nature of the clock cycles include the unknown initial state of the PLL, process variation, and temperature and voltage at the time of power-up. Under normal operations, the non-deterministic nature of the number of clock cycles is a “don't care” during power up. However, this non-deterministic characteristic causes problems during device testing, which is typically performed prior to shipping of the device. Testers compare the output of the PHY device against a known set of signal/bit patterns on a cycle by cycle basis. In a test environment, certain context-specific information (e.g., polarity) are not present.
FIG. 1
shows a NRZI (Non-return to Zero Interface) signal generated from a NRZ (Non-return to Zero) signal. As shown, there exists two possible initial states, state
1
and state
2
, for the NRZI signal. With NRZI signaling, only transitions and non-transitions convey information. In other words, a symbolic “1” is shown by a transition; a symbolic “0” is marked by no transition. Because the initial state of the NRZI signal is unknown, the incorrect (i.e., opposite) polarity may be employed in the transmission of the NRZI signals. In
FIG. 1
, an exemplary NRZ bit stream 01101001111001 is to be transmitted via a PHY device. State
1
assumes the initial level is 0; accordingly when the first 1 occurs at
101
, the signal transitions from 0 to 1. The next transition is at
103
corresponding to the second 1. The transition alternates from high to low and then low to high with subsequent transitions, as seen from transition points
105
,
107
,
109
,
11
1
, and
113
, until the end of the bit sequence. However, if the initial state is state
2
, the waveform exhibits the opposite polarity of the state
1
waveform. For example, at the first logical high point
101
, the waveform of state
2
transitions from high to low, in contrast to low to high of the state
1
waveform. Because these initial states are unknown, the tester may compare the wrong waveform against the output waveform of the PHY device, resulting in an invalid test result.
This problem is magnified with an MTL-3 signal, as shown in FIG.
2
. Although MTL-3 signaling is marked by three signal levels, there are four possible initial states. Two possible states stem from the zero level as in states
1
and
2
in which the waveform may transition up or down with the first occurrence of a 1 (
301
). With the exemplary bit stream, 0110100111001, the state
1
waveform transitions from 0 to 1 at
201
and
209
. At
203
and
211
, the transition is from 1 to 0. Further, and
213
, the state
1
waveform transitions from 0 to −1. A −1 to 0 transition occurs at
207
. The waveform of state
2
exhibits the opposite polarity of state
1
. For example, at
201
and
209
, the state
2
waveform transitions from 0 to −1, instead of 0 to 1 as in the case of state
1
. Regarding states
3
and
4
, the waveforms associated with these states are also opposite in polarity. State
3
has an initial level of 1; whereas, the waveform of state
4
begins with a −1. The state
3
waveform transitions from 1 to 0 at
215
and
221
, and from 0 to −1 at
217
and
223
. Transition from −1 to 0 occurs at
219
and
225
. At
220
, the transition is from 0 to 1. In state
4
, the transitions at these various points are opposite in polarity. That is, at
215
and
221
, the state
4
waveform transitions from −1 to 0. At
219
and
225
, the transition is from 1 to 0. The transition at
215
and
221
is from −1 to 0. The many possible initial polarity states create obstacles for testing while the PLL is stabilizing.
Because the NRZI signals and the MTL-3 signals possess multiple initial states, a test that incorrectly assumes a wrong state would yield inaccurate test results resulting in costly rejections of possibly properly functioning devices. A conventional approach attempts to address this problem by capturing all the various waveforms and performing “back-end” processing. Back-end logic refers to processing capabilities of other components or logic external to the PHY device as well as higher layer protocol processes. A major disadvantage with the conventional approach is that back-end processing is usually not feasible because of costs. Moreover, such an approach is time consuming, which translates into higher production costs.
SUMMARY OF THE INVENTION
There is a need for an arrangement for deterministically identifying the polarity of transmitted signals. There is also a need for an arrangement that reduces testing time by eliminating the requirement of performing back-end processing.
These and other needs are attained by the present invention, where a system for testing a networking device comprises a phase-locked loop (PLL) for generating a transmit clock signal in response to a basic clock signal. A reset extension circuit latches the basic clock signal and the transmit clock signal when the PLL stabilizes, and also generates a secondary reset signal. A physical layer (PHY) device generates encoded signals that represent a known valid bit pattern, wherein an initial pol
Advanced Micro Devices , Inc.
Ray Gopal C.
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