System for testing memory

Static information storage and retrieval – Read/write circuit – Testing

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371 212, G11C 700

Patent

active

060580550

ABSTRACT:
A system for efficiently testing and diagnosing memory arrays. One embodiment of the testing system efficiently identifies faulty memory cells in a memory chip, and subsequently removes the memory chip containing the faulty memory cells from the testing process. The system includes a testing module and an active port list which includes an identifier for each of a plurality of memory chips.

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