Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-01-26
2002-04-02
Niebling, John F. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06367066
ABSTRACT:
BACKGROUNDS OF THE INVENTION
1. Field of the Invention
The present invention relates to a circuit synthesizing method for LSIs and other types of integrated circuit devices and a circuit synthesizing device therefor, and more particularly to a circuit synthesizing method for enabling to synthesize a circuit with a small circuit area and to a circuit synthesizing device therefor.
2. Description of the Related Art
In recent years, LSIs in general have become larger in size and more complex in structure, leading to increasing demand for a system that can automate logical design in order to achieve higher efficiency in LSI design. As a means of realizing automated circuit design, a circuit synthesizing device has been provided for describing the behavior of a circuit using the hardware description language and then synthesizing a desired circuit according to the description that has been input.
In general, the design levels of circuit synthesizing devices consist of three types: behavior, RTL (Register Transfer Level), and logic.
The behavior level is the same level as considering an algorithm using the programming language, which is a design level for defining “what” behaves “how.” In behavior synthesis, scheduling is performed to determine the clock cycle and the procedure in which an operation is to be carried out on a behavior description. As a result of this scheduling, registers and functional units are allocated to variables and registers (i.e., binding) as necessary, and a state machine part for controlling the sequence of the operation is generated (i.e., state generation).
The RTL is a level one order below the behavior level. This level defines an architecture using such components as registers, functional units, and a state machine part, and clarifies the behaviors of individual clock cycles. Actions in RTL synthesis include inferring registers from descriptions, optimizing the operational sequence, and allocating resources.
The logic level is the lowest level, which expresses a design circuit using Boolean expressions, ASIC net lists, and so forth. The term “logic synthesis” usually refers to synthesis at the logic level.
It should be noted here that a functional unit very often has a large circuit area. When synthesizing a circuit, therefore, sharing of a functional unit that is not used simultaneously is desirable so that the area of a logic-synthesized circuit can be prevented from becoming too large.
As an example, we will take the case in which the following is input into a circuit synthesizing device as a behavior description:
unsigned a
1
(0:2),b
1
(0:2),c
1
(0:4);
unsigned a
2
(0:3),b
2
(0:3),c
2
(0:6);
if(cond)
{
cl=a
1
*b
1
;
}
else{
c
2
=a
2
*b
2
;
}
where a
1
and b
1
are unsigned variables that have 2 bits in total beginning with 0 bit, respectively; c
1
is an unsigned variable that has 4 bits in total beginning with 0 bit; a
2
and b
2
are unsigned variables that have 3 bits in total beginning with 0 bit, respectively; and c
2
is an unsigned variable that has 6 bits in total beginning with 0 bit. if(cond) else represents a process for selecting either of c
1
or c
2
, depending on the state specified by the value of cond. While the behavior description above shows an example of a description that performs an operation using unsigned variables, there are also descriptions that perform operations using signed variables.
When carrying out behavior synthesis based on a behavior description similar to the one shown above, conventional circuit synthesizing devices first find operations that are identical to each other but are not used in the same timing in the behavior description, and cause these operations to share the functional unit that are associated with them. Thus, in the behavior description shown above, the operations c
1
=a
1
*b
1
and c
2
=a
2
*b
2
are not carried out simultaneously, so a behavior is so synthesized as to carry out a
1
*b
1
and a
2
*b
2
separately, using the same functional unit (i.e., a multiplier).
One example of the results of behavior synthesis according to the procedure described above is shown in FIG.
7
.
FIG. 7
shows an example of the results of behavior synthesis that is output from a conventional circuit synthesizing device. In
FIG. 7
, “MUX” represents a multiplexer and “×” a multiplier (i.e., a functional unit).
As shown in
FIG. 7
, the number of multiplexers for switching variables to be input into a functional unit increases within a behavior-synthesized description. Even so, the area of the synthesized circuit can be reduced, since each multiplexer requires a smaller circuit area than a functional unit.
In conventional circuit synthesizing device, not only functional units but also registers are shared. Register sharing herein means to have one register to hold multiple pieces of data (variables) that are not processed in the same timing.
FIGS. 8 and 9
are data transfer diagrams showing an example of a register sharing method in a conventional circuit synthesizing device conducts. Of these,
FIG. 8
is a block diagram showing a register sharing method for signed variables, and
FIG. 9
showing a register sharing method for unsigned variables.
FIGS. 8 and 9
show the register sharing method that is conducted when transferring the value of the variable a
1
to the register c
1
and the value of the variable b
1
to the register c
2
, as follows:
c
1
=a
1
;
c
2
=b
1
;
Here, the registers c
1
and c
2
are implemented (i.e., shared) in one register (5 bits).
For example, as shown in
FIG. 8
, when transferring a
1
, which is a 2-bit signed variable, and b
1
, which is a 4-bit signed variable, to a common register (5 bit), bits are added to the variables a
1
and b
1
, respectively, in the numbers that are less than the bit count of the destination register. The multiplexer (MUX) then switches the variable to be transferred to the register, between a
1
and b
1
. Here, since the 0
th
bit of the variable a
1
and that of the variable b
1
are signed bits, the same data as the signed bits are inserted in the bits that are in short.
On the other hand, as shown in
FIG. 9
, for example, when transferring a
2
, which is a 4-bit unsigned variable, and b
2
, which is a 2-bit unsigned variable, to a common register (5 bit), bits are added to the variables a
2
and b
2
, respectively, in the numbers that are less than the bit count of the destination register, as with the case above for signed bits. The multiplexer (MUX) then switches the variable to be transferred to the register, between a
2
and b
2
. Here, since neither the variable a
2
nor b
2
holds a signed bit, data “0s” are inserted to the number of bits that are less than the number of bits in the register.
Thus, by conducting sharing for not only functional units but also for registers, a reduction in circuit area can be realized.
Generally, in a conventional circuit synthesizing device as described above, a behavior description is created by employing either operations using signed variables or operations using unsigned variables. However, for cases in which two types of operations, i.e., those using signed variables and those using unsigned variables, exist in the same behavior description, two types of functional units are required, making it impossible to share these functional units.
Thus, conventional circuit synthesizing devices have a drawback that the area of a circuit cannot be minimized in design, since full sharing of functional units and registers are not possible.
SUMMARY OF THE INVENTION
An objective of the present invention is to provide a circuit synthesizing device that can synthesize a circuit with a small circuit area by enabling sharing of functional units and registers even when both operations using signed variables and unsigned variables exist, and a method therefor.
Another objective of the present invention is to provide a circuit synthesizing device that can perform simulation of circuit behavior and other processes at a higher speed by using C language for descri
Foley & Lardner
NEC Corporation
Niebling John F.
Whitmore Stacy A
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