Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Counting – scheduling – or event timing
Reexamination Certificate
2000-08-03
2004-02-17
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Counting, scheduling, or event timing
C713S400000, C713S600000
Reexamination Certificate
active
06694446
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a microprocessor comprising a counter to measure a time interval as a function of an instructed value of counting and a counting clock signal.
The present invention relates more particularly to the synchronization of a microprocessor with an awaited asynchronous event, namely an event whose appearance or whose frequency of appearance is not synchronized with the internal clock of the microprocessor.
By way of an example,
FIG. 1
shows a sequence of asynchronous bits comprising conventionally a start bit bs, with a value of zero, followed by bits b
0
, b
1
, b
2
, b
3
, etc. constituting a message. These different bits are separated by constant time intervals Te corresponding to the period of an external clock signal He. Conventionally, the sequence of bits is received with a lag of one half-cycle of the clock signal He and comprises the following steps:
detecting the passage to 0 of the bit bs (event E
1
, appearance of the start bit),
when a time interval equal to Te/2has elapsed since the event E
1
(event E
2
), reading the bit bs and ascertaining that it is always equal to 0,
when a time interval equal to Te has elapsed since the event E
2
(event E
3
), reading the first bit b
0
of the message,
when a time interval equal to Te has elapsed since the event E
3
(event E
4
), reading the second bit b
1
of the message, etc.
FIG. 2
shows a schematic view of the implementation of this method by means of a microprocessor MP driven by a clock signal H
1
with a period T
1
that is not synchronized with the external clock signal He of the data transmission. At a port Pi, the microprocessor MP receives the sequence of bits of
FIG. 1. A
timer type counter TMR driven by a clock signal H
2
with a period T
2
records a counting instructed valve VAL when a loading signal LOAD is applied to it. When the counter TMR reaches the value 0 after the loading of the instructed value VAL, a flag FLZ of the counter goes to 0. This flag FLZ is applied to a port P
2
of the microprocessor. With this standard arrangement, the method described here above is expressed by the following programming sequence expressed in general terms:
(1) when the port P
1
goes to 0 (event E
1
, appearance of bit bs), loading the counter TMR with the counting instructed value VAL
1
, corresponding to a counting duration VAL
1
X
T
2
equal to Te/2,
(2) when the port P
2
(flag FLZ) goes to 0 (event E
2
), loading the counter with a counting instructed value VAL
2
, corresponding to a counting duration VAL
2
X
T
2
equal to Te, then reading the bit bs on the port P
1
and ascertaining that the bit is truly equal to 0,
(3) when the port P
2
goes to 0 (event E
3
), loading the counter with the counting instructed value VAL
2
and reading the bit b
0
at the port P
1
,
(4) when the port P
2
goes to 0 (event E
4
), loading the counter with the counting instructed value VAL
2
, then reading the bit b
1
at the port P
1
, . . . (and so on for the reading of the following bits).
In the above sequence, each new counting instructed value VAL
2
or VAL
2
is loaded immediately after the performance of each event and before the reading of the bits, in order to prevent a gradual lagging of the program with respect to the flow of asynchronous binary data. Despite this precaution, a temporal lag may arise between the time when the awaited event is actually reached and the time when this event is detected, namely the time when the “when” condition is met in the above program. This lag can be attributed to standard methods of event detection by polling or by interruption. It may be recalled that polling consists of a cyclical monitoring, by means of a program loop, of a point of the microprocessor, for example the ports P
1
and P
2
. This method requires the performance of several machine cycles (clock H
1
). The lag that appears between the performance of the event and its actual detection is random. It may be zero if the event occurs at the exact time of the polling of the port or, if not, it may be equal to one or more machine cycles. The method of detection by interruption consists of the association of a priority interruption signal with the event to be detected. When the event occurs, the microprocessor is made to go to an interruption subprogram for the loading of the counter. This subprogram includes a certain number of operations to be performed as well as a GOTO type instruction taking the operation to the rest of the program to be executed. This method, like the previous one, causes a lag between the time when the event occurs and the time when a new counting instructed value is actually loaded into the counter.
Furthermore, the loading of a counter is not an instantaneous operation and introduces an additional lag. Indeed, the microprocessor must read the counting instructed value, apply it to a data bus to present it to the input of the counter and then apply the loading signal LOAD: these operations could amount to several machine cycles.
In many applications, these various lags are negligible as compared with the time intervals Te/2 and Te, the clock H
1
of the microprocessor and the counting clock H
2
being identical and very fast as compared with the external clock He. However, in the context of the making of a microprocessor designed for chip cards and other portable electronic devices, these delays may become critical and lead to malfunctioning. In particular, the microprocessors of contactless chip cards receive digital data at high bit rates by magnetic induction at a rate which, although it is lower than that of the internal clock H
1
, is so high that the number of machine cycles that could be lost in a polling loop or in a interruption subprogram is not negligible. Furthermore, in these applications, the external clock signal He of the transmission as well as the counting clock signal H
2
, extracted from the carrier frequency Fac of an alternating magnetic field, may be faster than the internal cock H
1
of the microprocessor. The signals He and H
2
may for example be 13 MHz signals and the internal clock H
1
may be a 1 MHz signal.
The document EP 395 210 illustrates the drawbacks of the methods of event detection by interruption. In this document, data sent to a microprocessor is received in a FIFO stack of limited capacity. The filling of the FIFO stack is monitored by a counter which subtracts the number of “read in the stack” events from the number of “write in the stack” events. When the number of write operations minus the number of read operations crosses a certain threshold, an interrupt signal is sent in order to inform the microprocessor that the stack has to be emptied. This threshold is chosen to be below the capacity of the stack in order to take account of the relative slowness of the microprocessor in processing the interruption and to prevent an overflow of the stack. Furthermore, in this document, the data elements are received synchronously. Their reception does not require the monitoring of a port but the monitoring of the filling of the stack. The counter is an event counter (writing and reading of the stack) and is not a time counter.
SUMMARY OF THE INVENTION
Thus, it is a goal of the present invention to provide for a means enabling the precise synchronizing of a microprocessor with an asynchronous event or the synchronizing of a microprocessor with a clock that is faster than its internal clock.
This goal is attained by providing for a microprocessor of the above type, comprising wired logic detection means for the detection of at least one awaited event, these means being arranged to apply a signal for loading a counting instructed value to the counter as soon as the awaited event takes place.
Since these detection means are wired logic means and laid out so that the detection of one or more events prompts the updating of the counter, the lags caused by the standard methods of polling or interruption are overcome. Indeed, the reaction time of a wired logic circuit, namely the logic gate switching time, may be cons
Akin Gump Strauss Hauer & Feld & LLP
Du Thuan
Inside Technologies
Lee Thomas
LandOfFree
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