Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-09-19
2006-09-19
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
07111127
ABSTRACT:
One or more methods and systems of improving the performance of consecutive data stores into a cache memory are presented. In one embodiment, the method comprises writing data into a data array associated with at least a first store instruction while accessing a tag in a tag array associated with at least a second store instruction. In one embodiment, the method of processing consecutive data stores into a cache memory comprises updating a first data in a cache memory while concurrently looking up or identifying a second data in the cache memory. In one embodiment, a system for improving the execution of data store instructions of a CPU comprises a pipelined buffer using a minimal number of data entries, a data array used for updating data associated with a first store instruction, and a tag array used for looking up data associated with a second store instruction.
REFERENCES:
patent: 6763421 (2004-07-01), Luick
patent: 2002/0108022 (2002-08-01), Chen
patent: 2004/0103250 (2004-05-01), Alsup
Cheok Yook-Khai
Choung Chia-Cheng
So Kimming
Truong Bao-Binh
Broadcom Corporation
McAndrews Held & Malloy Ltd.
Nguyen Hiep T.
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