System for simultaneously accessing two portions of a shared mem

Details System for simultaneously accessing two portions of a shared mem System for simultaneously accessing two portions of a shared mem

1997-05-27

2000-04-11

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

711156, 711200, 711147, 710 19, 710 21, G06F 1200

Patent

active

060498560

ABSTRACT:
A memory system includes a data memory and a distinct cache status memory for storing status information regarding the data memory. A memory controller generates timing and control signals for accessing the data memory in a page mode while concurrently accessing the cache status memory in a word mode. In the preferred embodiment, the data memory is accessed in a four word per page mode while a read-modify-write operation is performed on an associated cache status memory. In order to conserve pins on the memory controller, the cache status memory shares a substantial portion of the address lines which are received by the data memory. Supplemental cache status address lines are generated by programmable control logic, which may be incorporated into the memory controller. Programmable control logic generates supplemental address lines based on the maximum number of data memory modules, the size of an addressed data memory module and the number of cache status columns. Thus any of a variety of data memory and cache status memory configurations may be employed.

REFERENCES:
patent: 4754270 (1988-06-01), Murauchi
patent: 4905184 (1990-02-01), Giridhar et al.
patent: 5164944 (1992-11-01), Benton et al.
patent: 5701516 (1997-12-01), Cheng et al.
patent: 5757817 (1998-05-01), Boyln et al.

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