System for simplifying the programmable memory to logic...

Details System for simplifying the programmable memory to logic... System for simplifying the programmable memory to logic...

2002-06-28

2004-06-08

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06748577

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the field of memory devices, and, more particularly, to a system for simplifying the programmable memory-to-logic interface in field programmable gate arrays (FPGAs).
BACKGROUND OF THE INVENTION
An FPGA is a semi-custom device including an array of generic cells or logic blocks each having a programmable function and which are surrounded by a programmable interconnect network. Inclusion of RAM blocks in the FPGA architecture saves valuable logic and routing resources. Memory intensive applications are accommodated within an FPGA with embedded RAM blocks. Also, many wide input/output functions may be handled by the RAM blocks, thus saving logic and interconnect resources.
Such RAM blocks are generally evenly distributed on the FPGA chip. An interconnect system is provided for the RAM to interface with other logic resources on chip. In U.S. Pat. No. 5,933,023 assigned to Xilinx, Inc., routing lines which access the logic blocks also access address, data, and control lines of the RAM blocks. This results in some routing flexibility between the RAM and other logic blocks, but at the same time offers a very complex model for the software tool. A number of constraints such as intra-bus net slack, general routing asymmetry, routing congestion, etc., may thus result.
SUMMARY OF THE INVENTION
The present invention provides a system for simplifying the interface between the embedded memory and the programmable logic blocks and input/output resources in an FPGA. The system may include an interface to isolate the general purpose routing architecture, or intra-programmable logic block (PLB) routing, from memory address lines, data lines, and control lines. Further, direct interconnects may be included for connecting the PLBs and input-output (IO) resources of the FPGA to the embedded memory or RAM.
The direct interconnects connect the input pins of the memory to outputs nearby of PLBs, and the output pins of the memory are directly connected to the inputs of PLBs in the vicinity thereof. The direct interconnects to/from the memory are not a part of the general routing resources of the FPGA. As such, they do not hamper the symmetric routing fabric or lines for the logic resources or the PLBs.
The memory may have a plurality of multiplexers and de-multiplexers connected to its input and output pins, respectively. The inputs to the multiplexers may be output from various PLBs, the same PLB, or from IO pads. Further, the outputs from the de-multiplexers are connected to the PLB inputs or IO resources. Further, the PLBs interact with the memory through programmable tappings or switches which provide the interface.
The above system may further include devoted bus-based routing for connecting data and address lines to combine the memory blocks and implement larger memories. This reduces configuration register/flip-flop count with respect to a net-to-net route. The registers internal to the memory blocks may be eliminated by utilizing the registers/flip-flops of the PLBs for latching signals sent to or received from the memory, thereby saving significant chip area.
The registers internal to the memory may include input registers, output registers, or both. The internal registers/flip-flops of the PLBs may also receive inputs from the general purpose routing. The internal elements of the PLBs may include a look up table (LUT), and an internal flip-flop may also be used for other functionality independent of the memory interface. The registers/flip-flops are selectively bypassed for the case when unregistered memory inputs and outputs are required. The memory may be ROM or RAM, for example.
The connectivity of the PLBs and IO resources with the general purpose routing architecture coexists with the interface to the embedded memory. The output registers internal to the memory blocks may be eliminated by utilizing the registers of the PLBs for latching the output data from the memory, thereby saving significant chip area.
The present invention further provides a method for simplifying the interface between the embedded memory and the programmable logic blocks and input output resources in an FPGA. The method may include isolating the general purpose routing architecture (or intra-PLB routing) from memory address lines, data lines, and control lines. The method may further include connecting the PLBs and IO resources of the FPGA to the embedded memory (or memories) using multiple dedicated direct interconnects.
More particularly, the method may also include connecting, via direct interconnects, the input pins of the memory to outputs of PLBs in the vicinity of the memory blocks. Further, output pins of the memory are directly connected to the inputs of PLBs in the vicinity thereof. It should be noted that the direct interconnects are not a part of the general routing resources of the FPGA and, thus, do not hamper the symmetric routing for the logic resources or the programmable logic blocks (PLBs).
The above method may be particularly applicable to a single port memory including a plurality of multiplexers and de-multiplexers connected to the input and output pins thereof, respectively. In such case, the method may include connecting inputs to the multiplexer to outputs from multiple PLBs, a same PLB, or input-output (IO) pads/routing. The method may further include connecting outputs from the de-multiplexer to PLB inputs or IO resources.
The above method thus allows for the restriction of interaction between the PLBs and memory through programmable devices. The above method may further include devoted bus-based routing for connecting data and address lines to combine the memory blocks and, thus, implement larger memories. Again, this reduces configuration register/flip-flop count with respect to a net-to-net route.
The registers internal to the memory blocks present in prior art devices may be eliminated by utilizing the registers/flip-flops of the PLBs for latching signals sent to or received from the memory, thus saving significant chip area. The registers internal to the memory may include input registers, output registers, or both. The internal registers/flip-flops of the PLBs may also receive inputs from the general purpose routing.
The internal elements of the PLBs including the LUT and the internal flip-flop may also be used for other functionality independently of the memory interface. The method may also include selectively bypassing the registers/flip-flops for the case when unregistered memory outputs are required. The memory may be ROM or RAM, for example.
The connection of the PLBs and IO resources to the general purpose routing architecture coexists with the interface to the embedded memory. The output registers internal to the memory blocks may be eliminated by utilizing the registers of the PLBs for latching the output data from the memory, thus saving significant chip area.


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