System for simplifying layout processing

Details System for simplifying layout processing System for simplifying layout processing

2005-03-28

2009-02-03

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07487490

ABSTRACT:
A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts by applying layout processing to handle imperfections such as jogs in integrated circuit design layouts. The layout processing may be applied to jogs in the original integrated circuit design layout or jogs created post-design by process biases, as well as design rule check and Boolean processes or process compensation.

REFERENCES:
patent: 6523162 (2003-02-01), Agrawal et al.
patent: 6625801 (2003-09-01), Pierrat et al.
patent: 7159197 (2007-01-01), Falbo et al.
patent: 7181721 (2007-02-01), Lippincott et al.

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