Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral adapting
Reexamination Certificate
1997-11-17
2001-01-16
Lee, Thomas C. (Department: 2782)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral adapting
C710S058000, C710S071000, C327S091000, C327S094000, C341S100000
Reexamination Certificate
active
06175885
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a device for the conversion of a series signal received in the form of a low-amplitude, high-frequency differential signal into a number, n, of parallel signals. The invention can be applied more particularly in the field of serial data reception.
The use of a differential signal is particularly suited to the transmission of data elements in series links. Disturbances, such as distortions and noise, that appear during the transmission of the signal act without distinction on the two signals that form the differential signal, and therefore do not cause any deterioration in the information to be transmitted which constitutes the difference between the two signals.
The conversion device as described in the present application is used to convert a high-frequency and low-amplitude differential signal representing a string of bits into n parallel logic signals.
2. Description of the Prior Art
Known conversion devices generally have a differential input to receive a series differential signal with a period T. This signal is applied to the inputs of a differential amplifier so as to transpose it to two logic levels Vdd and Vss. The converted signal is then sampled by a set of n master/slave registers which are parallel-connected to the output of the amplifier. The sampling period of the registers is taken to be equal to nT and the sampling signals of the n master/slave registers are staggered with respect to one another by a time interval equal to the period T of the differential signal. Thus, at the output of the n master/slave registers, there are obtained n samples of the series signal staggered by a time interval T.
For example, for the conversion of a string of bits received at a frequency of 100 KHz in 10-bit words, the conversion device has ten master/slave registers that sample the string of bits at a frequency of 10 KHz and the sampling instants of these different registers are staggered by 10 &mgr;s with respect to each other.
However, this type of device does not work satisfactorily when the frequency of the string of bits received is high, in the range of one gigahertz. At this frequency, the differential amplifier introduces an instability in the time base of the signal received and therefore shifts the edges of the series signal. This phenomenon is accentuated when the differential signal applied to the input of the amplifier contains noise in common mode. The result is that the samples obtained at the output of the master/slave registers may, in certain cases, no longer represent the initial string of bits.
SUMMARY OF THE INVENTION
An aim of the invention, therefore, is a conversion device by which it is possible to do away with the need to use a differential amplifier to transpose the input differential signal to two logic levels.
Thus, an object of the invention is a device for the series-to-parallel conversion of a series signal received in the form of a low-amplitude, high-frequency differential signal with a period T, this device being designed to convert the series signal into n parallel logic signals. The device comprises a series input consisting of a first input terminal and a second input terminal, the differential signal being received between the first and second input terminals, a parallel output consisting of n output terminals to deliver the n parallel signals, and a clock circuit to deliver n clock signals with a period nT that are staggered with respect to one another by a time interval equal to T. The device further comprises n sample-and-hold units which obtain samples of the series signals staggered with respect to one another by a time interval equal to T, each sample-and-hold unit comprising a first input and a second input respectively connected to the first and second input terminals, a control input to receive one of the n clock signals and an output connected to one of the output terminals of the parallel output to deliver a sample. The sample-and-hold units simultaneously amplify the samples of the series signal.
To obtain this amplification and transpose the samples to two logic levels, static memory cells are used as sample-and-hold units. Thus, each sample-and-hold has a master part to sample the series signal and amplify the resulting samples, and a slave part to store the samples.
According to a preferred embodiment, the master part comprises a first connection gate connected, on the one hand, to the first input of the sample-and-hold unit and, on the other hand, to the input of a first inverter and to the output of a second inverter. The master part further comprises a second connection gate connected, on the one hand, to the second input of the sample-and-hold unit and, on the other hand, to the output of the first inverter and to the input of the second inverter. The first and second connection gates are controlled by a first pair of control signals coming from the clock signal applied to the control input of the sample-and-hold unit.
Furthermore, the slave part of the sample-and-hold unit preferably has a third connection gate connected, on the one hand, to the input of the first inverter of the master part and, on the other hand, to the input of a third inverter, the output of the fourth inverter and the first output of the sample-and-hold unit. The slave part further comprises a fourth connection gate connected, on the one hand, to the output of the first inverter and, on the other hand, to the output of the third inverter and the input of the fourth inverter. The third and fourth connection gates are controlled by a second pair of control signals coming from the clock signal applied to the control input of the sample-and-hold unit.
In most cases, the conversion of the series signal received cannot be limited solely to a resetting of the signal at two logic levels and to the sampling of this signal. It is also necessary to resynchronize the received signal, namely to place the edges of the sampling signals in phase with the clock signal associated with the received signal.
The technique used to resynchronize the received series signal with a frequency f consists of sampling the signal at the frequency 2f. Since the received signal represents a string of bits, each bit is thus sampled twice. The aim of this technique is to identify the instants of transition between the bits of the received signal and then adapt the sampling of the signal as a function of these instants.
Since the invention makes it possible not to introduce any instability into the time base of the signal received at the time of amplification, it is particularly suited to conversion devices comprising means for the recovery of the clock signal from the received series signal. This is why, according to one preferred embodiment, the clock circuit delivers n additional clock signals with a period nT, giving a total of 2n clock signals, with a period nT, that are staggered with respect to one another by a time interval equal to T/2.
The conversion device further comprises n additional sample-and-hold units to obtain a total of 2n samples of the series signal staggered with respect to one another by a time interval equal to T/2, a logic processing and decision circuit to process the 2n samples of the series signal and determine whether the series signal has been accurately sampled with respect to the time periods. The processing and decision circuit comprises 2n inputs connected to the outputs of the 2n sample-and-hold units, n outputs connected to the n output terminals of the device and one control output delivering a control signal to the clock circuit to stagger the clock signals until an accurate sampling of the series signal is obtained.
According to another embodiment of the invention, a device for converting a series input signal to a parallel output signal is disclosed. The device comprises a first plurality of sampling devices for obtaining a number of first samples of the series signal, the first plurality of sampling devices being controlled by a timing signal of a clock d
Couteaux Pascal
D'Hoe Michel
Le Bihan Jean-Claude
Marbot Roland
Mottini Francis
Cao Chun
Galanthay Theodore E.
Lee Thomas C.
Morris James H.
SGS-Microelectronics S.A.
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