System for selectively connecting CPU bus to DMAC bus when acces

Details System for selectively connecting CPU bus to DMAC bus when acces System for selectively connecting CPU bus to DMAC bus when acces

1997-06-05

1999-10-19

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Direct memory accessing

710108, 710 22, 710 25, G06F 1328

Patent

active

059681454

ABSTRACT:
A data processing unit capable of solving a conventional problem in that a CPU cannot acquire the right of using a bus as long as a DMAC (Direct Memory Access Controller) has that right, and hence the operating ratio of the CPU reduces. A CPU bus is kept disconnected from the DMAC bus as long as the CPU disables the access request to a memory connected to the DMAC bus, and is connected to a DMAC bus in response to the access request unless the DMAC has the right of using a DMAC bus.

REFERENCES:
patent: 4999769 (1991-03-01), Costes et al.
patent: 5542110 (1996-07-01), Minagawa
patent: 5566345 (1996-10-01), Ostrowski
patent: 5613162 (1997-03-01), Kabenjian
patent: 5805930 (1998-09-01), Rosenthal

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