System for representing the logical and physical information...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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Details

C716S030000, C716S030000, C716S030000, C345S649000, C345S650000

Reexamination Certificate

active

07073149

ABSTRACT:
A floor planner tool for integrated circuit design which provides tools and displays for a designer to create a floor plan to define desired placement of circuits defined in a logical netlist by creating a physical hierarchy comprised of nested physical blocks (pblocks). Each pblock is a data structure which contains data which defines which circuits from the logical netlist are assigned to it. Each pblock stands alone and can be input to a place and route tool without the rest of the physical hierarchy. Each pblock data structure contains pointers to the circuits on the netlist assigned to that pblock, identifies other pblocks nested within it and contains a list of pins for the instances within the pblock. Net data structures in the physical hierarchy define which nets are connected to which pins.

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Wang, Maogang et al., “Multi-Million Gate FPGA Physical Design Challenges” ICCAD 2003, Nov. 11-13, 2003, pp. 891-898, available from Cadence Design Systems, www.cadence.com, 2655 Seely Avenue, San Jose, California 95134.

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