System for reducing the latency of exclusive read requests...

Details System for reducing the latency of exclusive read requests... System for reducing the latency of exclusive read requests...

2008-05-20

2008-05-20

Elmore, Stephen (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S142000, C711S143000, C711S156000, C711S207000, C710S317000

Reexamination Certificate

active

07376799

ABSTRACT:
A symmetric multi-processing system for processing exclusive read requests. The system includes a plurality of cell boards, each of which further includes at least one CPU and cache memory, with all of the cell boards being connected to at least one crossbar switch. The read-latency reducing system includes write-through cache memory on each of the cell boards, a modified line list on each crossbar switch having a list of cache lines that have been modified in the cache memory of each of the cell boards, and a cache coherency directory on each crossbar switch for recording the address, the status, and the location of each of the cache lines in the system. The modified line list is accessed to obtain a copy of a requested cache line for each of the exclusive read requests from the cell boards not containing the requested cache line.

REFERENCES:
patent: 5887146 (1999-03-01), Baxter et al.
patent: 7051150 (2006-05-01), Naumann et al.
patent: 2003/0131203 (2003-07-01), Berg et al.
patent: 2005/0086438 (2005-04-01), Peterson et al.

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