System for reducing power consumption in a microprocessor...

Electrical computers and digital processing systems: support – Computer power control – Power conservation

Reexamination Certificate

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Details

C712S209000, C712S210000

Reexamination Certificate

active

10989090

ABSTRACT:
The present disclosure illustrates a system for reducing power consumption in a computer processor. Included is a 16-bit instruction decoder for decoding instructions with 16-bit words, a 32-bit instruction decoder for decoding instructions with 32-bit words, a word length select for indicating a present instruction's word length, and a first selector for routing the instruction into the 16-bit decoder when the present instruction is 16-bits long. The first selector is also configured to route a previous instruction into the 16-bit decoder, maintaining the 16-bit decoder's present state. A second selector is configured to route the instruction into the 32-bit decoder when the present instruction is 32-bits long. The second selector is also configured to route a past instruction into the 32-bit decoder to maintain the 32-bit decoder's present state.

REFERENCES:
patent: 6978358 (2005-12-01), Francis
patent: 7017030 (2006-03-01), Oldfield et al.
patent: 2004/0199747 (2004-10-01), Shelor
patent: 2004/0205322 (2004-10-01), Shelor
patent: 2004/0236926 (2004-11-01), Tran et al.

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