System for reducing number of lookups in a branch target...

Electrical computers and digital processing systems: processing – Processing control – Branching

Reexamination Certificate

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Reexamination Certificate

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07640422

ABSTRACT:
A technique for reducing lookups to a branch target address cache (BTAC) is disclosed. In this technique, a branch target address is retrieved from the BTAC in response to a miss in looking up an instruction address in an instruction cache (I-cache). The branch target address is associated with the instruction address. The branch target address retrieved from the BTAC is stored in the I-cache. With this disclosed technique, subsequent instruction addresses are looked up in the I-cache, nonparallel to the BTAC, thus saving power by reducing needless BTAC lookups.

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patent: 5136697 (1992-08-01), Johnson
patent: 5774710 (1998-06-01), Chung
patent: 6324643 (2001-11-01), Krishnan
patent: 6427192 (2002-07-01), Roberts
patent: 6651162 (2003-11-01), Levitan
patent: 2005/0132173 (2005-06-01), Moyer
IBM Technical Disclosure Bulletin, Improving Instruction Cache Branch Prediction with Target Addresses, V 36, I 7, pp. 497-498, Jul. 1, 1993.
Johnson, Mike, Superscalar Microprocessor Design, Prentice Hall, 1991, pp. 71-77.
Webster's Ninth New Collediate Dictionary, Merriam-Webster Inc., 1990, pp. 96.

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