Electrical computers and digital processing systems: memory – Address formation
Reexamination Certificate
1997-07-24
2002-05-28
Patel, Ajit (Department: 2662)
Electrical computers and digital processing systems: memory
Address formation
C711S207000
Reexamination Certificate
active
06397316
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to a device for connecting a computer system to a computer network, and more particularly to a method and an apparatus for reducing bus overhead in communications between a computer system and a network interface device through which the computer system communicates with a high speed packet-switched network.
2. Related Art
The advent of computer networking has given rise to devices that connect computer systems to packet-switched data networks. These devices (known as network interface controllers, or NICs) typically include interfaces to both the computer system and the packet-switched data network, as well as a buffer memory for buffering packets of data in transit between the computer system and the packet-switched data network. The interface to the computer system typically connects to a bus within the computer system, such as a PCI bus, through which data is transferred between the computer system memory and the NIC. As computer networks and NICs greatly increase in performance, communications across this bus can become an impediment to achieving high performance in communications between the computer system and the packet-switched data network.
Three methods can be used to communicate between a computer system and a device such as a NIC. (1) Programmed I/O (PIO) operates by including explicit I/O commands in the application programs executed by the computer system. PIO can be implemented with a simple hardware and operating system design. However, it places a tremendous burden on the application program to explicitly manage communications between the computer system and the NIC. (2) Shared memory can be used to facilitate communications between the NIC and the computer system. In a shared memory system, the NIC and the computer system communicate by writing to and reading from a shared memory that exists in both the address space of the computer system and the address space of the NIC. This again leads to a simple hardware and operating system implementation, and a clean interface between the computer system and the NIC. However, it again places a burden on the application program to explicitly manage communications between the computer system and the NIC. (3) Finally, direct memory access (DMA) can be used to transfer data between the NIC and the memory of the computer system. DMA operates by allowing the NIC to perform bus operations to directly access the memory of the computer system in order to transfer data between the computer system and the NIC. A DMA system requires considerable complexity in hardware and operating system design. However, it relieves the application program of the burden of explicitly managing communications between the computer system and the NIC.
DMA transfers between computer systems and NICs are commonly accomplished using the scatter-gather technique. In scatter-gather, a bus master device in the NIC is first instructed to obtain a command block from the memory of a host computer system. At a minimum, the command block contains a list of physical addresses for blocks within the host system memory that are to be copied to the DMA device. The command block also contains a count of the number of fragments in the command block and the overall length of the data contained in the fragments pointed to by the command block. The DMA device parses the command block, extracting the address of each fragment, and transfers the fragments from the host memory to the DMA device. This process is repeated for each fragment listed in the command block until all of the data described by the command block is copied to the DMA device.
A significant performance bottleneck in using the scatter-gather technique for transferring data to a high speed network is the translation from virtual to physical addresses. Peripheral devices, such as a NIC, cannot use virtual memory addresses to effect the transfers, because the hardware to implement the virtual-to-physical address translation is typically located inside the CPU. This means that conversion between virtual and physical addresses must take place before transfers between a computer system and a NIC can take place. This conversion can take a great deal of time and consume a significant amount of the computer system's processing power. When data is passed to a device driver for transmission to the NIC, the driver first performs a virtual-to-physical address conversion for each buffer fragment passed down to it from the application layers above. It is possible for each buffer fragment to straddle physical pages of the memory system. Thus, more than one physical address may correspond to each virtual address converted. Consequently, several virtual-to-physical address conversions may be required for each buffer of data that is transferred from the computer system to the NIC. This can be very time-consuming because each virtual-to-physical address translation can take from tens to hundreds of CPU cycles to accomplish.
Another significant performance impediment associated with the scatter-gather technique is its command block nature. Peripheral devices such as NICs typically connect to computer systems through a peripheral interconnect bus, such as the PCI bus. In order to transfer data to or from the computer system, devices connected to the bus contend for control of the bus. Once a device is granted control of the bus, it drives bus signal lines to transfer data to or from the computer system. The performance impediment stems from the number of times a NIC must contend for the peripheral interconnect bus when transferring data using the scatter-gather technique. Under ideal circumstances for scatter-gather, bus contention to transfer data between a NIC and an attached computer system will occur three times per buffer transferred: first, when the computer system informs the NIC that a buffer is available for its use; second when the NIC reads the command block describing the buffer; and third when the NIC transfers data to or from the buffer. In typical scenarios, at least two buffer fragments will be described in each command block. As a result, there will be at least four contentions instead of three. These additional contentions create opportunities for other devices to obtain control of the bus and thus delay transfers initiated by the NIC.
What is needed is a method for performing DMA between a computer system and a NIC which is free from the overhead of performing virtual to physical address translations and minimizes the number of bus transactions required to initiate the DMA transfer process.
SUMMARY
The present invention provides a method and an apparatus for transferring data between a computer system and a network interface card that avoids virtual-to-physical address translations. The computer system allocates blocks of memory during system initialization for storing data in transit between the computer system and the NIC, and the physical addresses of these blocks of memory are stored in a table on the NIC. Consequently, address conversion is performed only once, when the memory is allocated. When a request to transfer data to the NIC is received from the upper layers, the device driver copies the data from the upper layers into the next available memory block. The device driver then formats a command and passes it to the NIC for processing. Data transfer commands are communicated to the NIC through a packet descriptor command (PDC), which is a 32-bit value subdivided into fields that completely describe the data transfer operation. The PDC contains a small ordinal value that indexes a table in the NIC, which includes a set of physical addresses of buffers preallocated by the computer system in the computer system memory. These buffers are used for storing data in transit to the NIC. The PDC also contains the length of the buffer to be copied to or from the NIC. The present invention also allows for multiple packets to be formatted into buffers and then subsequently transferred to the NIC in a single I/O operation.
The present invent
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Patel Ajit
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