System for reduced power consumption by phase locked loop...

Details System for reduced power consumption by phase locked loop... System for reduced power consumption by phase locked loop...

2006-04-25

2006-04-25

Browne, Lynne H. (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C713S300000, C713S320000, C713S322000, C713S324000, C713S330000, C345S204000, C345S211000, C345S214000, C375S376000, C365S227000, C331S049000, C331S060000, C331S074000

Reexamination Certificate

active

07036032

ABSTRACT:
A system and method are provided for reducing power consumption within a video processing portion of a system. Activity associated within a video-processing portion of a personal digital assistant is analyzed. As reduced activity is identified, power conservation modes are implemented. In a normal mode of operation, a clock signal generated through an external oscillator is provided to a phase locked loop (PLL). An output clock signal from the PLL is then provided to several dividers to generate system clock signals. In a reduced mode of operation, the output clock from the external oscillator is provided to a divider, bypassing the PLL. Video processing components then use clock signals based on the external oscillator. In a suspend mode, both the PLL and the external oscillator are disabled.

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U.S. Appl. No. 10/083,917, Mizuyabu, et al., Pending.
U.S. Appl. No. 10/083,875, Mizuyabu, et al., Pending.

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