Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Correction for skew – phase – or rate
Reexamination Certificate
2005-06-14
2005-06-14
Lee, Thomas (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Correction for skew, phase, or rate
C370S503000, C375S372000, C710S057000
Reexamination Certificate
active
06907541
ABSTRACT:
A system for reliably receiving data includes a memory, write logic, and read logic. The write logic receives data and an unreliable clock signal and writes the data to the memory using the unreliable clock signal. The read logic generates a gapped clock signal and reads the data from the memory using the gapped clock signal. The read logic generates the gapped clock signal by turning on and off a constant local clock signal.
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Padmanabhan Ramesh
Sindhu Pradeep
Verwillow Eric M.
Harrity & Snyder LLP
Juniper Networks, Inc.
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